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Showing results 1 to 22 of 22

Issue Date	Title / Author(s) / Citation	File
2016-03	A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single <i>LC</i>-VCO for 2G-4G Multistandard Cellular Transceivers Yoon, Heein; Lee, Yongsun; Lim, Younghyun; Tak, Geum-Young; Kim, Hong-Teuk; Ho, Yo-Chuol; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.51 No.3, pp.614-625	DOI
2016-08	A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector Choi, Seojin; Yoo, Seyeon; Lim, Younghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.51 No.8, pp.1878-1889	DOI
2017	An External-Capacitor-less Low-Dropout Regulator with Less than-36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate Lim, Younghyun; Lee, Jeonghyun; Park, Suneui; Choi, Jaehyouk 2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)
2017-11	An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Song, Seong-Sik; Kim, Hong-Teuk; Lee, Ockgoo; Choi, Jaehyouk IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.25 No.11, pp.3006-3018	DOI
2018	153 fS<sub>RMS</sub>-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-<i>LC</i>-Hybrid Injection-Locked Clock Multiplier Choi, Seojin; Yoo, Seyeon; Lee, Yongsun; Jo, Yongwoo; Lee, Jeonghyun; Lim, Younghyun; Choi, Jaehyouk 2018 IEEE SYMPOSIUM ON VLSI CIRCUITS, pp.185-186
2018	An External-Capacitor-Less High-PSR Low-Dropout Regulator Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate Lim, Younghyun; Lee, Jeonghyun; Park, Suneui; Choi, Jaehyouk 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.299-300
2018	A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk ESSCIRC 2018 - IEEE 44TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pp.210-213
2018	A-31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers Yoon, Heein; Kim, Juyeop; Park, Suneui; Lim, Younghyun; Lee, Yongsun; Bang, Jooeun; Lim, Kyoohyun; Choi, Jaehyouk 2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC), pp.366-+
2018-07	A 65-nm CMOS 2 x 2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations Lim, Kyoohyun; Lee, Sanghoon; Lee, Yongha; Moon, Byeongmoo; Shin, Hwahyeong; Kang, Kisub; Kim, Seungbeom; Lee, Jinhyeok; Lee, Hyungsuk; Shim, Hyunchul; Sung, Chulhoon; Park, Kumyoung; Lee, Garam; Kim, Minjung; Park, Seokyeong; Jung, Hyosun; Lim, Younghyun; Song, Changhun; Seong, Jaehyeon; Cho, Heechang; Choi, Jaehyouk; Lee, Jongryul; Han, Sangwoo IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.7, pp.1960-1976	DOI
2018-09	An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique Lim, Younghyun; Lee, Jeonghyun; Park, Suneui; Jo, Yongwoo; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.9, pp.2675-2685	DOI
2019	A 0.5V-V<sub>IN</sub>, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer Lee, Jeonghyun; Bang, Jooeun; Lim, Younghyun; Choi, Jaehyouk 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C130-C131
2019	A 140fs<sub>rms</sub>-Jitter and-72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk 2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.62, pp.490-+
2019	A 76fs<sub>rms</sub> Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization Kim, Juyeop; Yoon, Heein; Lim, Younghyun; Lee, Yongsun; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.62, pp.258-+
2019-04	An Ultra-Low-Jitter 22.8-GHz Ring-<i>LC</i>-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114 Choi, Seojin; Yoo, Seyeon; Lee, Yongsun; Jo, Yongwoo; Lee, Jeonghyun; Lim, Younghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.4, pp.927-936	DOI
2019-12	An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.12, pp.3466-3477	DOI
2019-12	A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single-VCO-Based Edge-Racing Time Quantizer Lee, Jeonghyun; Bang, Jooeun; Lim, Younghyun; Yoo, Seyeon; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk IEEE SOLID-STATE CIRCUITS LETTERS, Vol.2 No.12, pp.305-308	DOI
2020	A 170MHz-Lock-In-Range and-253dB-FoM<sub>jitter</sub>, 12-to-14.5GHz Subsampling PLL with a 150μW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; Choi, Jaehyouk 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.280-+
2021	A 104fs<sub>rms</sub>-Jitter and-61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique Kim, Juyeop; Jo, Yongwoo; Lim, Younghyun; Seong, Taeho; Park, Hangi; Yoo, Seyeon; Lee, Yongsun; Choi, Seojin; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.448-+	DOI
2021-01	A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.56 No.1, pp.298-309	DOI
2022-02	A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.2, pp.480-491	DOI
2023-12	A Wideband LO Generator for 5G FR1 Bands Using a Single <i>LC</i>-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier Jo, Yongwoo; Kim, Juyeop; Shin, Yuhwan; Park, Hangi; Hwang, Chanwoong; Lim, Younghyun; Choi, Jaehyouk IEEE Journal of Solid-State Circuits, Vol.58 No.12, pp.3338-3350	DOI
2024-02	A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Kim, Juyeop; Jo, Yongwoo; Park, Hangi; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk IEEE Journal of Solid-State Circuits, Vol.59 No.2, pp.424-434	DOI