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Showing results 1 to 29 of 29

Issue Date	Title / Author(s) / Citation	File
1998	Partial bus-invert coding for power optimization of system-level bus Shin, Youngsoo; Chae, Soo-Ik; Choi, Kiyoung International Symposium on Low Power Electronics and Design 1998, August 10-12, pp.127-132
1998-04	Reduction of bus transitions with partial bus-invert coding Shin, Young Soo; Chae, Soo-Ik; Choi, Kiyoung Electronics Letters- IEE, 1998, 34, (7), pp.642-643
2001	Partial Bus-Invert Coding for Power Optimization of Application-Specific Systems Shin, Young Soo; Choi, Kiyoung; Chae, Soo-Ik IEEE Trans. VLSI Syst., vol. 9, pp.377-383	view file DOI
2002-03	An efficient simulation environment for the design of networked Bluetooth devices Ahn, Yongjin; Kim, Dae Hong; Lee, Sunghyun; Park, Sanggyu; Yoo, Sung Joo; Choi, Kiyoung; Chae, Soo-Ik Design Automation for Embedded Systems, v.8, no. 2-3, pp. 119-138	DOI
2003	An efficient simulation environment and simulation techniques for Bluetooth device design Ahn, Yongjin; Kim, Dae Hong; Lee, Sunghyun; Park, Sanggyu; Yoo, Sung Joo; Choi, Kiyoung; Chae, Soo-Ik Design Automation for Embedded Systems, vol. 8, pp. 119-138	DOI
2009	Leakage Power Reduction of Functional Units in Processors having Zero-Overhead Loop Counter Park, Hanmin; Paek, Jong Kyung; Lee, Jinho; Choi, Kiyoung 2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), pp.492-495	DOI
2012	An Adaptive Routing Algorithm for 3D Mesh NoC with Limited Vertical Bandwidth Zhu, Mingyang; Lee, Jinho; Choi, Kiyoung 2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC), pp.18-23
2012	Memory-Aware Mapping and Scheduling of Tasks and Communications on Many-Core SoC Lee, Jinho; Choi, Kiyoung 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.419-424
2013	Deflection Routing in 3D Network-on-Chip with TSV Serialization Lee, Jinho; Lee, Dongwoo; Kim, Sunwook; Choi, Kiyoung 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.29-34
2013	A Deadlock-Free Routing Algorithm Requiring No Virtual Channel on 3D-NoCs with Partial Vertical Connections Lee, Jinho; Choi, Kiyoung 2013 SEVENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS 2013)
2013-10	Deflection Routing in 3D Network-on-Chip with Limited Vertical Bandwidth Lee, Jinho; Lee, Dongwoo; Kim, Sunwook; Choi, Kiyoung ACM Transactions on Design Automation of Electronic Systems, Vol.18 No.4, p. 50	DOI
2013-11	Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint Lee, Jinho; Chung, Moo-Kyoung; Cho, Yeon-Gon; Ryu, Soojung; Ahn, Jung Ho; Choi, Kiyoung IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.32 No.11, pp.1748-1761	DOI
2014-12	Tree-mesh heterogeneous topology for low-latency NoC Han, Sungju; Lee, Jinho; Choi, Kiyoung ACM International Conference Proceeding Series, Vol.23-26-September-2014, pp.19-24	DOI
2015-01	THOR: Orchestrated Thermal Management of Cores and Networks in 3D Many-Core Architectures Lee, Jinho; Ahn, Junwhan; Choi, Kiyoung; Kang, Kyungsu 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.773-778	DOI
2015-09	REDELF: An Energy-Efficient Deadlock-Free routing for 3D NoCs with partial vertical connections Lee, Jinho; Kang, Kyungsu; Choi, Kiyoung ACM Journal on Emerging Technologies in Computing Systems, Vol.12 No.3, p. 26	DOI
2016	Buffered Compares: Excavating the Hidden Parallelism Inside DRAM Architectures with Lightweight Logic Lee, Jinho; Ahn, Jung Ho; Choi, Kiyoung PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), pp.1243-1248
2016-04	A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers Kim, Kyounghoon; Lin, Helin; Choi, Jin Young; Choi, Kiyoung Pattern Recognition, Vol.52, pp. 1-16	DOI
2017-06	Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares Lee, Jinho; Chung, Jongwook; Ahn, Jung Ho; Choi, Kiyoung IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.25 No.6, pp.1793-1806	DOI
2017-08	ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator Lee, Jinho; Kim, Heesu; Yoo, Sungjoo; Choi, Kiyoung; Hofstee, H. Peter; Nam, Gi-Joon; Nutter, Mark R.; Jamsek, Damir Proceedings of the VLDB Endowment, Vol.10 No.12, pp.1706-1717	DOI
2018-10	Deep neural networks with weighted spikes Kim, Jaehyun; Kim, Heesu; Huh, Subin; Lee, Jinho; Choi, Kiyoung Neurocomputing, Vol.311, pp.373-386	DOI
2019-01	Cell Division: Weight Bit-Width Reduction Technique for Convolutional Neural Network Hardware Accelerators Park, Hanmin; Choi, Kiyoung 24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019), pp.286-291	DOI
2019-01	Network Recasting: A Universal Method for Network Architecture Transformation Yu, Joonsang; Kang, Sungbum; Choi, Kiyoung THIRTY-THIRD AAAI CONFERENCE ON ARTIFICIAL INTELLIGENCE / THIRTY-FIRST INNOVATIVE APPLICATIONS OF ARTIFICIAL INTELLIGENCE CONFERENCE / NINTH AAAI SYMPOSIUM ON EDUCATIONAL ADVANCES IN ARTIFICIAL INTELLIGENCE, pp.5701-5708
2019-05	Aging Gracefully with Approximation Kim, Jongho; Kim, Heesu; Amrouch, Hussam; Henkel, Joerg; Gerstlauer, Andreas; Choi, Kiyoung 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), p. 8702120	DOI
2019-06	Acceleration of DNN Backward Propagation by Selective Computation of Gradients Lee, Gunhee; Park, Hanmin; Kim, Namhyung; Yu, Joonsang; Jo, Sujeong; Choi, Kiyoung PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), pp.1-16	DOI
2019-07	VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks Kim, Jaehyun; Lee, Chaeun; Kim, Jihun; Kim, Yumin; Hwang, Cheol Seong; Choi, Kiyoung 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), p. 8824902	DOI
2019-10	Fast Simulation Method for Analog Deep Binarized Neural Networks Lee, Chaeun; Kim, Jaehyun; Kim, Jihun; Hwang, Cheol Seong; Choi, Kiyoung 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), pp.293-294	DOI
2019-10	An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network Lee, Chaeun; Kim, Jaehyun; Choi, Kiyoung 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), pp.259-260	DOI
2021	GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent Kim, Heesu; Park, Hanmin; Kim, Taehyun; Cho, Kwanheum; Lee, Eojin; Ryu, Soojung; Lee, Hyuk-Jae; Choi, Kiyoung; Lee, Jinho 2021 27TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA 2021), Vol.2021-February, pp.249-262	DOI
2022-07	ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator Kim, Namhyung; Park, Hanmin; Lee, Dongwoo; Kang, Sungbum; Lee, Jinho; Choi, Kiyoung IEEE Transactions on Computers, Vol.71 No.7, pp.1537-1550	DOI