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Issue Date	Title / Author(s) / Citation	File
2022-09	A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing Yun, Daeho; Lee, Eonhui; Jung, Woosong; Kim, Kahyun; Beak, Kyung-Min; Kim, Jihee; Lee, Hyun-Bae; Ko, Byeongseon; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3749-3753	DOI
2019-09	A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.9, pp.2501-2512	DOI
2018	A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk ESSCIRC 2018 - IEEE 44TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pp.210-213
2021-06	A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System Lee, Jihee; Lee, Kyoung-Rog; Eovino, Benjamin E.; Park, Jeong Hoan; Liang, Luna Yue; Lin, Liwei; Yoo, Hoi-Jun; Yoo, Jerald IEEE Journal of Solid-State Circuits, Vol.56 No.6, pp.1910-1923	DOI
2021	A 365fs<sub>rms</sub>-Jitter and-63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third-Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.442-+	DOI
2019-06	A 370-fJ/b, 0.0056 mm(2)/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop Ko, Han-Gon; Shin, Soyeong; Kye, Chan-Ho; Lee, Sang-Yoon; Yun, Jaekwang; Jung, Hae-Kang; Lee, Duobock; Kim, Suhwan; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C94-C95	DOI
2021-04	A 3D MODEL-BASED APPROACH FOR FITTING MASKS TO FACES IN THE WILD Hong, Je Hyeong; Kim, Hanjo; Kim, Minsoo; Nam, Gi Pyo; Cho, Junghyun; Ko, Hyeong-Seok; Kim, Ig-Jae Proceedings - International Conference on Image Processing, ICIP, pp.235-239	DOI
2016-02	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Talegaonkar, Mrunmay; Anand, Tejasvi; Elkholy, Ahmed; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.51 No.2, pp.428-439	DOI
2019-06	A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS Park, Kwanseo; Lee, Kwangho; Cho, Sung-Yong; Lee, Jinhyung; Hwang, Jeongho; Choo, Min-Seong; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C194-C195	DOI
2014-06	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo-Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858446	DOI
2014-06	A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter Talegaonkar, M.; Anand, T.; Elkholy, A.; Elshazly, A.; Nandwana, R.K.; Saxena, S.; Young, B.; Choi, Woo Seok; Hanumolu, P.K. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858392	DOI
2010-11	A 4.78 μs Dynamic Compensated Inductive Coupling Transceiver for Ubiquitous and Wearable Body Sensor Network Lee, Seulki; Yoo, Jerald; Yoo, Hoi-Jun IEICE Transactions on Communications, Vol.E93B No.11, pp.2892-2900	DOI
2011-03	A 40fJ/c-s 1 V 10 bit SARADC with Dual Sampling Capacitive DAC Topology Kim, Binhee; Yan, Long; Yoo, Jerald; Yoo, Hoi-Jun JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.11 No.1, pp.23-32	DOI
2022	A 410-GHz Detector using AC-coupled Substrate-Integrated Waveguide Slot Antenna in CMOS Anas, Md Toaha; Azmeen-ur-Rahman, Saad; Choi, Wooyeol PROCEEDINGS OF THE 2022 IEEE TEXAS SYMPOSIUM ON WIRELESS AND MICROWAVE CIRCUITS AND SYSTEMS (WMCS)	DOI
2022	A 430GHz CMOS Concurrent Transceiver Pixel Array for High Angular Resolution Reflection-Mode Active Imaging Zhu, Y.; Byreddy, P.R.; Dong, S.; Kenneth, K.O.; Choi, W. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2022-February, pp.86-88	DOI
2017-05	A 45-75MHz 197-452μW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS Zhu, Junheng; Mahalley, Makrand; Shu, Guanghua; Choi, Woo Seok; Nandwana, Romesh Kumar; Elkholy, Ahmed; Sahoo, Bibhudatta; Hanumolu, Pavan Kumar Proceedings of the Custom Integrated Circuits Conference, Vol.2017-April, p. 7993679	DOI
2015	A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica-Delay-Cells Kim, Mina; Choi, Seojin; Choi, Jaehyouk 2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS)
2011	A 45nm SOI-CMOS PLL with a Wideband LC-VCO Lee, Kun-Seok; Beck, Sungho; Jeon, Hamhee; Yoon, Youngchang; Choi, Jaehyouk; Lee, Chang-Ho; Kenney, J. Stevenson 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)
2021-11	A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS Lee, Kwangho; Jung, Woosong; Ju, Haram; Lee, Jinhyung; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2023-05	A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation Kim, Kahyun; Yun, Daeho; Baek, Kyungmin; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE International Symposium on Circuits and Systems proceedings, Vol.2023-May, p. 190917	DOI

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