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Advanced Device Architectures for Organic Logic Elements and Nonvolatile Memory Cells : 유기 논리 소자와 비휘발성 메모리를 위한 고성능 소자 구조

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Authors

김민회

Advisor
이신두
Major
공과대학 전기·컴퓨터공학부
Issue Date
2013-02
Publisher
서울대학교 대학원
Keywords
organic thin-film transistorinterfacial interactionschevron gate configurationdual gateorganic inverterferroelectric nonvolatile memory
Description
학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 이신두.
Abstract
Organic electronics has attracted much attention due to their low-cost, large-area, and flexible electronic device applications such as flexible displays, radio frequency identification tags, and sensor sheets. Especially, numerous approaches for the high performance organic thin-film transistors (OTFTs) have been studied due to their driving and switching capability. Recently, for the commercialization of the OTFTs, not only a single device but electronic functional blocks which consist of various types of OTFTs are studied. One of the great ways to obtain both high performance of single device and integration of various OTFTs is to design new device architectures. In order to fabricate new device structures, new patterning process is required, since the conventional patterning process such as photolithography cannot be used for organic materials due to the damage of organic materials during photolithography.
In this thesis, new device physics and process technology of the advanced device architectures are presented for the enhancement of the performance of the single OTFT and the realization of the electronic functional blocks. Especially, it is presented that the underlying physical mechanism comes from the interface between the gate insulator and the organic semiconductor. First, the general overview of the organic electronics and the operation principles of the OTFTs are introduced. It is demonstrated how the parameters of the OTFTs, organic inverters, and ferroelectric OTFTs affect the device performance.
In the viewpoint of the single device, it is presented how device architectures have an influence on the performance of the OTFTs. In order to obtain saturated high drain current at low voltage, the chevron gate configuration is designed and fabricated. Furthermore, the short channel effect and current modulation is physically analyzed. For the high performance OTFTs with the n-type polymer semiconductor, the dual-gate architecture is introduced. The dual-gate architecture allows the threshold voltage and mobility to be controlled by the biasing the counter gate electrode.
Next, combination of the two different types of the OTFTs for the novel electronic functional blocks is demonstrated. The interface between First, the control mechanism for interfacial charges in an OTFT by the introduction of a surface polarized layer (SPL), which generates a transverse dipolar field, is demonstrated. The concept of such SPL enables to develop a high noise-margin full-swing unipolar inverter on a single substrate. The transverse dipolar field of the SPL of a fluorinated polymer which is placed between the organic semiconductor and the gate insulator plays an essential role in the accumulation of holes at the interface due to the surface dipoles of the fluorinated polymer. Owing to the interfacial holes, the OTFT with the SPL operates in a depletion mode and its magnitude lies between the on-current and off-current of a conventional OTFT with no SPL. This directly allows the high noise-margin and the full-swing capability of an organic unipolar inverter with zero gate load OTFT.
Second, paraelectric/ferroelectric bilayer architectures in ferroelectric OTFT for nonvolatile memory array are demonstrated. The paraelectric buffer layer (PBL) on the ferroelectric layer plays an essential role in screening the electric field of the ferroelectric dipole and reducing the roughness of the insulator. It is found that the OTFTs with the bilayer structure exhibit high switching on-off current ratio and low memory on-off current ratio. Through the selective formation of the bilayer structure, the ferroelectric memory OTFTs are integrated with the selection OTFTs having the bilayer structure. Through this configuration, ferroelectric memory array without crosstalk between memory cells and voltage-readable multistate ferroelectric memory cell are demonstrated.
In conclusion, through this thesis, it is presented that the advanced device architectures enhanced the performance of the single device and realized the electronic functional blocks. Approaches of increasing the drain current and controlling the threshold voltage, introduced here, are expected to provide a basis for realizing many applications of the OTFTs. Moreover, the device physics and the integration technique for the organic inverter and ferroelectric circuit will provide a platform for the organic logic elements and nonvolatile memory cells.
Language
English
URI
https://hdl.handle.net/10371/118879
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