Nano-structured RRAM for Ultra High Density and Low Power RRAM

Abstract

The IT industry has grown explosively since the emergence of a variety of mobile devices that make us handle information anytime and anywhere. The demand of large-capacity information storage device has increased with this trend. Currently, the development of the three-dimensional stacked NAND flash memory is nestled into the mainstream of a large-capacity memory. On the other hand, in order to achieve excellent memory performance of much faster, less power consumption, and higher density, the research of new memories are being actively conducted as a alternative to the NAND flash memory. Among these memories, RRAM has attracted much attention as one of the most promising candidates that may replace the conventional memory due to its simple structure, good scalability, high-speed operation, and low energy consumption. In spite of the above-mentioned advantages, RRAM suffers from high reset current, poor reliability such as large variation in set/reset voltages and LRS/HRS resistances. It is struggling to commercialize. In this thesis, a study was carried out to solve the problems through a structural change of RRAM. In the introduction, the basic structure and operation principle of RRAM is described. Especially, advantage of nitride-based RRAM with Si bottom electrode is also described. And, the methods to solve the issues of RRAM is introduced. Searching for the optimal combination of material and Applying additional treatment to the device can improve the memory characteristics. Structural approach to improve performance can be a method for fundamentally solving the problem. First, the basic bipolar resistive switching characterstics and the conduction mechanism are analyzed in large size cell of silicon nitride-based RRAM with Si bottom electrode. Then, the cross-point array of the RRAM that is based on these materials is demostrated for the first time. In the fabricated cross-point RRAM cell, analysis of active area scaling effect is performed. It is found that the switching voltage increases with the scaling down of the active area. In order to reduce the switching voltage and improve the memory performance, a new device structure having a nano-cone shaped silicon is proposed and is applied to the cross-point array of RRAM for the first time. By using simulation tool, it is verified that the electric field concentration effect occurs at the sharp point of nano-cone and the electric field is concentrated locally. These results imply that the position occuring resistive switching phenomenon is confined at the end of nano-cone and the posibility of the reduced switching voltage and uniform switching behavior can be achieved. Finally, the feasibility of low power operation in the proposed device is successfully verified by the fabrication and the measurement.