Design of Digital PLL/CDR with Advanced Digital Controller

Abstract

This paper presents a design methodology of digital PLL/CDR with various digital controllers. In comparison with analog approaches, digital techniques can circumvent inherent design constraints of analog-based timing circuits, thereby achieve such as non-linear transfer, gear shifting (adaptive damping technique), fast-locking algorithm and so on. First, this paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is, the PLLs second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs, the proposed PLL implements the peaking-free loop filter directly in digital domain without requiring additional components. A time-to-digital converter (TDC) is implemented as, a set of three binary phase-frequency detectors that oversample the timing error with time-varying offsets, achieving a linear TDC gain and PLL bandwidth insensitive to the jitter condition. And a 9.2-GHz digitally-controlled LC oscillator (DCO) with transformer-based tuning realizes a predictable DCO gain set by a ratio between two digitally-controlled currents. The prototype 9.2-GHz-output digital PLL fabricated in a 65nm CMOS demonstrates a fast settling time of 1.58-μs with 690-kHz bandwidth. The PLL has a 3.477-psrms divided clock jitter and -120dBc/Hz phase noise at 10-MHz offset while dissipating 63.9-mW at a 1.2-V supply. Second, the proposed high-order clock and data recovery(CDR) employs tracking aid to track frequency modulated data using spread-spectrum clocking(SSC) to mitigate steady-state jitter characteristic. This paper describes the implementation of the tracking aid to achieve accurate estimation of the time instants. Instead of the noise sensitive differentiator used in previous works, the proposed architecture uses an integrator that is more resilient to noise or disturbance and more accurate. The design of the architecture fully implemented in digital achieves SSC timing errors less than < 10 cycles, locking time < 15 ms overall CDR jitter of 0.12UIpp.