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Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC
Cited 8 time in
Web of Science
Cited 12 time in Scopus
- Authors
- Issue Date
- 2007
- Publisher
- Springer Verlag
- Citation
- Design Automation for Embedded Systems 11(4):249-283
- Abstract
- Emerging embedded systems require heterogeneous multiprocessor SoC architectures
that can satisfy both high-performance and programmability. However, as the complexity
of embedded systems increases, software programming on an increasing number
of multiprocessors faces several critical problems, such as multithreaded code generation,
heterogeneous architecture adaptation, short design time, and low cost implementation. In this paper, we present a software code generation flow based on Simulink to address these
problems. We propose a functional modeling style to capture data-intensive and controldependent
target applications, and a system architecture modeling style to seamlessly transform
the functional model into the target architecture. Both models are described using
Simulink. From a system architecture Simulink model, a code generator produces a multithreaded
code, inserting thread and communication primitives to abstract the heterogeneity
of the target architecture. In addition, the multithread code generator called LESCEA applies
the extensions of dataflow based memory optimization techniques, considering both
data and control dependency. Experimental results on aMotion-JPEG decoder and an H.264
decoder show that the proposed multithread code generator enables easy software programming
on different multiprocessor architectures with substantially reduced data memory size
(up to 68.0%) and code memory size (up to 15.9%).
- ISSN
- 0929-5585 (print)
1572-8080 (Online)
- Language
- English
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