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nMOS Reversible Energy Recovery Logic for Ultra-Low-Energy Applications

Cited 37 time in Web of Science Cited 47 time in Scopus
Authors
Lim, Junho; Kim, Donggyu; Chae, Soo-Ik
Issue Date
2000
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE J. Solid-State Circuits, vol. 35, pp.865-875
Keywords
6-phase clocked power generatoradiabatic circuitbootstrapped switchenergy consumptionnMOS reversible energy recovery logic
Abstract
We propose a new fully reversible adiabatic logic,
nMOS reversible energy recovery logic (nRERL), which uses
nMOS transistors only and a simpler 6-phase clocked power. Its
area overhead and energy consumption are smaller, compared
with the other fully adiabatic logics. We employed bootstrapped
nMOS switches to simplify the nRERL circuits. With the simulation
results for a full adder, we confirmed that the nRERL circuit
consumed substantially less energy than the other adiabatic
logic circuits at low-speed operation. We evaluated a test chip
implemented with 0.8- m CMOS technology, which included
a chain of nRERL inverters integrated with a clocked power
generator. The nRERL inverter chain of 2400 stages consumed
the minimum energy at dd = 3 5 V at 55 kHz, where the
adiabatic and leakage losses are about equal, which is only 4.50%
of the dissipated energy of its corresponding CMOS circuit at
dd = 09 V. In conclusion, nRERL is more suitable than the
other adiabatic logic circuits for the applications that do not
require high performance but low energy consumption.
ISSN
0018-9200
Language
English
URI
https://hdl.handle.net/10371/16274
DOI
https://doi.org/10.1109/4.845190
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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