Influence of line-edge roughness on multiple-gate tunnel field-effect transistors

Abstract

The influence of fin-line-edge roughness (fin-LER) and gate-LER on multiple-gate (MG) tunnel field-effect transistors (TFETs) has been investigated compared with MG MOSFETs by using full three-dimensional technology computer-aided design (TCAD) simulation. From simulation results, two interesting results have been observed. First, MG TFETs show much less severe gate-LER than MG MOSFETs, which means that only fin-LER can be considered when evaluating the total LER of MG TFETs. Second, TFETs show similar to 3x more LER improvement than MOSFETs when their structures are changed from double-gate (DG) to triple-gate (TG) ones. Our findings provide the useful design guidelines of variation-tolerant TFETs. (C) 2017 The Japan Society of Applied Physics