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Superconductor Computing for Neural Networks

Cited 16 time in Web of Science Cited 20 time in Scopus
Authors

Ishida, Koki; Byun, Ilkwon; Nagaoka, Ikki; Fukumitsu, Kosuke; Tanaka, Masamitsu; Kawakami, Satoshi; Tanimoto, Teruo; Ono, Takatsugu; Kim, Jangwoo; Inoue, Koji

Issue Date
2021-05
Publisher
Institute of Electrical and Electronics Engineers
Citation
IEEE Micro, Vol.41 No.3, pp.19-26
Abstract
The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural unit due to a lack of understanding about its potentials and limitations at the architectural level. This article provides the design principles for SFQ-based architectural units with an extremely high-performance neural processing unit (NPU). To achieve our goal, we developed and validated a simulation framework to identify critical architectural bottlenecks in designing a performance-effective SFQ-based NPU. We propose SuperNPU, which outperforms a conventional state-of-the-art NPU by 23 times in terms of computing performance and 1.23 times in power efficiency even with the cooling cost of the 4K environment.
ISSN
0272-1732
URI
https://hdl.handle.net/10371/195625
DOI
https://doi.org/10.1109/MM.2021.3070488
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