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A 76fs<sub>rms</sub> Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization
Cited 42 time in
Web of Science
Cited 0 time in Scopus
- Authors
- Issue Date
- 2019
- Publisher
- IEEE
- Citation
- Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.62, pp.258-+
- ISSN
- 0193-6530
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- There are no files associated with this item.
Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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