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A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique
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Cited 1 time in Scopus
- Authors
- Issue Date
- 2018
- Publisher
- IEEE
- Citation
- 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.307-308
- Abstract
- A low-jitter, low-reference spur switched-loop-filter (SLF) PLL that uses a fast phase-error correction (FPEC) technique emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM) is presented. Even for a high multiplication factor (i.e., 64), the proposed SLF PLL concurrently achieved ultra-low jitter and low reference spur. The prototype was fabricated in a 65-nm CMOS process. The RMS-jitter, the FOM, and the reference spur were measured as 378 fs, -242 dB, and -71 dBc, respectively.
- ISSN
- 2153-6961
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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