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A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Jaehyouk | - |
dc.contributor.author | Kim, Woonyun | - |
dc.contributor.author | Lim, Kyutae | - |
dc.date.accessioned | 2024-04-25T04:12:38Z | - |
dc.date.available | 2024-04-25T04:12:38Z | - |
dc.date.created | 2024-04-25 | - |
dc.date.issued | 2012-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.20 No.5, pp.969-973 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://hdl.handle.net/10371/199441 | - |
dc.description.abstract | This paper proposes a new reference-spur elimination architecture for a charge-pump-based phase locked loop (PLL) using an edge interpolation technique. By utilizing a charge-distribution mechanism on the control voltage of the voltage-controlled oscillator, the proposed architecture is capable of suppressing high-order harmonics of the reference spur, as well as a fundamental spur. In implementation, the eight-stage edge interpolator achieved more than 16-dB additional spur suppression. In addition, the harmonics of the reference spur within a 104-MHz frequency offset, the location of the eighth harmonic of the reference spur, were dramatically suppressed. The prototype PLL was fully integrated in a 0.18-mu m CMOS technology, which occupies a 670 mu m x 640 mu m active chip area. Additional circuits for the edge interpolator consumes less than one-fifth of the total area and power. | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TVLSI.2011.2129602 | - |
dc.citation.journaltitle | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.wosid | 000302640200018 | - |
dc.identifier.scopusid | 2-s2.0-84859793559 | - |
dc.citation.endpage | 973 | - |
dc.citation.number | 5 | - |
dc.citation.startpage | 969 | - |
dc.citation.volume | 20 | - |
dc.description.isOpenAccess | N | - |
dc.contributor.affiliatedAuthor | Choi, Jaehyouk | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordAuthor | Edge interpolator | - |
dc.subject.keywordAuthor | phase locked loop (PLL) | - |
dc.subject.keywordAuthor | reference spur | - |
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- College of Engineering
- Department of Electrical and Computer Engineering
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