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A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL
Cited 17 time in
Web of Science
Cited 29 time in Scopus
- Authors
- Issue Date
- 2012-05
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.20 No.5, pp.969-973
- Abstract
- This paper proposes a new reference-spur elimination architecture for a charge-pump-based phase locked loop (PLL) using an edge interpolation technique. By utilizing a charge-distribution mechanism on the control voltage of the voltage-controlled oscillator, the proposed architecture is capable of suppressing high-order harmonics of the reference spur, as well as a fundamental spur. In implementation, the eight-stage edge interpolator achieved more than 16-dB additional spur suppression. In addition, the harmonics of the reference spur within a 104-MHz frequency offset, the location of the eighth harmonic of the reference spur, were dramatically suppressed. The prototype PLL was fully integrated in a 0.18-mu m CMOS technology, which occupies a 670 mu m x 640 mu m active chip area. Additional circuits for the edge interpolator consumes less than one-fifth of the total area and power.
- ISSN
- 1063-8210
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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