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A robust latch-type sense amplifier using adaptive latch resistance
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- Authors
- Issue Date
- 2010
- Publisher
- IEEE
- Citation
- 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010, pp.182-185
- Abstract
- A latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS technology showing the SM improvement of 6% to 15% at various supply voltages.
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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