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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties
Cited 4 time in
Web of Science
Cited 4 time in Scopus
- Authors
- Issue Date
- 2019-03
- Publisher
- IEEE Computer Society
- Citation
- IEEE Design and Test, Vol.36 No.2, pp.81-87
- Abstract
- Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University
- ISSN
- 2168-2356
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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