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A 13-bit 70MS/s SAR-Assisted 2-bit/cycle Cyclic ADC with Offset Cancellation and Slack-Borrowing Logic
Cited 1 time in
Web of Science
Cited 1 time in Scopus
- Authors
- Issue Date
- 2023
- Publisher
- European Solid-State Circuits Conference
- Citation
- European Solid-State Circuits Conference, Vol.2023-September, pp.281-284
- Abstract
- This paper presents an energy and area-efficient successive approximation register (SAR)-assisted cyclic analog-to-digital converter (ADC) architecture. The proposed hybrid ADC combines a 2-bit/cycle cyclic ADC with a slack-borrowing coarse SAR ADC. The proposed multiply-by-one cyclic ADC achieves low-power and 2-bit/cycle operation without any extra hardware cost. The simultaneous amplifier and comparator offset cancellation mitigates the 2nd-stage cyclic ADC offset. Clocked at 70MS/s, the proposed ADC consumes 0.88mW, yielding FoMS and FoMW of 175dB and 6.9fJ/conv, respectively.
- ISSN
- 1930-8833
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Related Researcher
- College of Engineering
- Department of Electrical and Computer Engineering
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