Publications

Detailed Information

A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering

Cited 0 time in Web of Science Cited 7 time in Scopus
Authors

Choi, Woo Seok; Anand, Tejasvi; Shu, Guanghua; Hanumolu, Pavan Kumar

Issue Date
2013-06
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C280-C281
Abstract
A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows variable JTRAN bandwidth from 5MHz to 40MHz. © 2013 JSAP.
URI
https://hdl.handle.net/10371/203214
Files in This Item:
There are no files associated with this item.
Appears in Collections:

Related Researcher

  • College of Engineering
  • Department of Electrical and Computer Engineering
Research Area DRAM-PIM, High Bandwidth Memory Interface, O Links, Performance Modeling for I

Altmetrics

Item View & Download Count

  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Share