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Reduction in energy consumption by bootstrapped n MOS switches inreversible adiabatic CMOS circuits

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Authors
Lim, Junho; Kim, Donggyu; Chae, Soo-Ik
Issue Date
1999-12
Publisher
Institution of Engineering and Technology
Citation
IEE Proc., Circuits Devices Syst., 1999, 146, (6), pp. 327-333
Abstract
For ultra-low-energy applications, hootstrapped reversible-energy-re cove^ logic (bRERL)
is proposed, which is a reversible adiabatic CMOS logic and requires an 8-phase clock. In hRERL,
each transmission gate was replaced by a bootstrapped nMOS switch in the logic functional blocks of
tRERI,. Using SPICE simulations, it was confirmed that the bRERL circuit consumed less energy
and occupied less area than the tRERL circuit. The authors integrated a hRERL inverter chain with
its 8-phase, clocked power generator in a test chip, which was fabricated with 0 . 6 C~M OS
technology. They also confirmed that they could minimise the energy consumption in the hRERL
circuit by reducing the operating frequency until adiabatic and leakage losses were equal.
ISSN
1350-2409
Language
English
URI
https://hdl.handle.net/10371/21017
DOI
https://doi.org/10.1049/ip-cds:19990686
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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