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A mixed-level virtual prototyping environment for SystemC-based design methodology
Cited 1 time in
Web of Science
Cited 3 time in Scopus
- Authors
- Issue Date
- 2009
- Publisher
- Elsevier
- Citation
- Microelectronics Journal. 40(7) 1082-1093.
- Keywords
- SystemC ; Transactionlevelmodel ; Channel ; Architecturetemplate ; Virtual prototype
- Abstract
- Weproposeaflexiblemixed-levelvirtualprototypingenvironment,wheremodelsindifferent
abstraction levelssuchastransactionlevel,register-transferlevel,andsoftwarelevelcanbeco-
simulatedtogether.Intheproposedenvironment,thedesignersshouldcaptureatransactionlevel
systemmodelbeforehardware–softwarepartitioning,fromwhichmixed-levelvirtualprototyping
models canberefinedwithpre-definedandpre-verifiedcommunicationprimitives.Weexplainseveral
techniquesemployedintheenvironmentsuchasIDportsforsoftwaretemplateefficiency,abstraction
adaptersinSystemCformixedlevelsimulation,andtrace-drivensimulationforfasterperformance
evaluation.Moreover,transactionleveldescriptionsinSystemCcanbecompiledandexecutedas
softwaretogetherwiththeDEOS,whichisanoperatingsystemthatprovidesSystemCAPIs.We
comparedthesimulationspeedofseveralmixed-levelvirtualprototypesofaH.264decodertoshowthe
effectiveness oftheproposedenvironment.
- ISSN
- 0026-2692
- Language
- English
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