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Cache Optimization for H.264/AVC Motion Compensation

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Authors
Yoon, Sangyong; Chae, Soo-Ik
Issue Date
2008-12
Publisher
Institute of Electronics, Information and Communication Engineers
Citation
IEICE Trans. Information and Systems, vol. E91-D no. 12 pp.2902-2905
Keywords
cacheH.264motion compensationmemory bandwidthDDR
Abstract
In this letter, we propose a cache organization that substantially
reduces the memory bandwidth of motion compensation (MC) in
the H.264/AVC decoders. To reduce duplicated memory accesses to P and
B pictures, we employ a four-way set-associative cache in which its index
bits are composed of horizontal and vertical address bits of the frame buffer
and each line stores an 8 × 2 pixel data in the reference frames. Moreover,
we alleviate the data fragmentation problem by selecting its line size that
equals the minimum access size of the DDR SDRAM. The bandwidth of
the optimized cache averaged over five QCIF IBBP image sequences requires
only 129% of the essential bandwidth of an H.264/AVC MC.
ISSN
0916-8532
Language
English
URI
https://hdl.handle.net/10371/21377
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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