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Hardware implementation of inter-processor communication in MPSoCs for multimedia applications

DC Field Value Language
dc.contributor.authorKoo, Moonmo-
dc.contributor.authorChae, Soo-Ik-
dc.date.accessioned2010-04-01T02:00:46Z-
dc.date.available2010-04-01T02:00:46Z-
dc.date.issued2007-07-
dc.identifier.citationInternational Technical Conference on Circuits/Systems, Computers and Communicationsen
dc.identifier.urihttps://hdl.handle.net/10371/62296-
dc.description.abstractIn this paper we present a scalable and flexible architecture
that implements inter-processor communication (IPC) synchronization
among FIFO channels for multimedia applications. We also compare it
to the simple mail-box architecture, especially for tasks of finer
granularity. With experimental results we confirmed the proposed
architecture is suitable for various cases including a Motion JPEG
example.
en
dc.language.isoenen
dc.titleHardware implementation of inter-processor communication in MPSoCs for multimedia applicationsen
dc.typeConference Paperen
dc.contributor.AlternativeAuthor구문모-
dc.contributor.AlternativeAuthor채수익-
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Others_전기·정보공학부
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