S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Chemical and Biological Engineering (화학생물공학부) Journal Papers (저널논문_화학생물공학부)
Investigation of various copper seed layers for copper electrodeposition applicable to ultralarge-scale integration interconnection
- Kim, Jae Jeong; Kim, Soo-Kil; Lee, Chang Hwa; Kim, Yong Shik
- Issue Date
- American Vacuum Society
- The Journal of Vacuum Science and Technology B Microelectronics and Nanometer Structures 21, 33-38
- copper; electrodeposition; circuit interconnections; electroless deposited coatings; electrodeposits; electrical resistivity; metallic thin films; surface topography; organic compounds; annealing; adhesion; integrated circuit metallisation
- As a superior substituent for the chemical-vapor deposition and physical-vapor deposition ~PVD!
Cu processes in an ultralarge-scale integrated interconnection, electrodeposition on two kinds of
electroless-plated Cu seed layers was investigated. Co~II! and formaldehyde were used as reducing
agents for each electroless plating. Two samples of electroless-plated seed layers had relatively
higher resistivity due to rough and irregular grains and weakly developed ~111! texture, which are
peculiarities of electroless plating. However, the Cu electrodeposited onto the electroless-plated
seed showed reasonably good characteristics in resistivity, impurity level, crystalline structure, and
surface roughness compared to those on the conventional PVD Cu seed. For the gap filling in the
damascene structure, the electroless seed layer plating using formaldehyde and the subsequent
electrodeposition on a patterned wafer showed an excellent filling profile without any voids or
keyholes. After 400 °C annealing in a N2 atmosphere, adhesion between the Cu/barrier interfaces of
electrodeposited copper on the two electroless-plated seeds was highly improved.
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