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Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures

Cited 22 time in Web of Science Cited 39 time in Scopus
Authors
Kim, Suhwan; Choi, Chang Jun; Jeong, Deog-Kyoon; Stephen V., Kosonocky; Park, Sung Bae
Issue Date
2008-01
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 197-205
Keywords
CMOS technology scalingdevice/circuitground-bounce noisepower-gating technique
Abstract
Power gating is one of the most effective techniques
in reducing leakage power, which increases exponentially with
device scaling. However, large ground bounces during abrupt
changes of power mode may cause unwanted transitions in neighboring
circuits, which should still be operating normally. We
analyzed this ground-bounce noise and reduced it with novel
power-gating structures that utilize holistic integrated devicecircuit-
architecture approaches. We control the amount of charge
in the intermediate nodes of the circuit that passes through the
sleep transistors during the wake-up transition and stabilize the
minimum virtual power supply voltage required for data retention.
These techniques have been proven in silicon using 65-nm
bulk CMOS technology.
ISSN
0018-9383
Language
English
URI
https://hdl.handle.net/10371/68009
DOI
https://doi.org/10.1109/TED.2007.911067
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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