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A Fast-Acquisition PLL using Split Half-Duty Sampled Feedforward Loop Filter

Cited 4 time in Web of Science Cited 6 time in Scopus
Authors
Shin, Woo-Yeol; Kim, Manho; Hong, Gi-Moon; Kim, Suhwan
Issue Date
2010-08
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. 1856-1859
Keywords
Acquisition timeloop filterpattern jitterphase locked loop (PLL)
Abstract
Abstract — We reduce the pattern jitter and acquisition
time of a phase-locked loop (PLL) by adopting the split halfduty
sampled feedforward loop filter. A prototype designed
and fabricated in a 0.18􀈝m standard CMOS technology has a
40% lower acquisition time than a PLL without operating in
fast acquisition mode. Its peak-to-peak jitter is 26% less than
that of a PLL with a conventional 2nd-order RC loop filter.
ISSN
0098-3063
Language
English
URI
https://hdl.handle.net/10371/70061
DOI
https://doi.org/10.1109/TCE.2010.5606337
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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