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A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
Cited 38 time in
Web of Science
Cited 47 time in Scopus
- Authors
- Issue Date
- 2010-11
- Citation
- IEEE Journal of Solid State Circuits, vol.45, no.11, pp. 2300-2311
- Keywords
- Adaptive gain control ; all-digital phase locked loop (ADPLL) ; bang-bang phase and frequency detector (BBPFD) ; false position method ; fractional divider ; frequency search
- Abstract
- Abstract—A 0.3–1.4 GHz all-digital phase locked loop (ADPLL)
with an adaptive loop gain controller (ALGC), a 1/8-resolution
fractional divider and a frequency search block is presented. The
ALGC reduces the nonlinearity of the bang-bang phase-frequency
detector (BBPFD), reducing output jitter. The fractional divider
partially compensates for the large input phase error caused by
fractional-N frequency synthesis. A fast frequency search unit
using the false position method achieves frequency lock in 6 iterations
that correspond to 192 reference clock cycles. A prototype
ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC,
a fractional divider, and a digital logic implementation of a frequency
search algorithm was fabricated in a 0.13- m CMOS logic
process. The core occupies 0.2 mm and consumes 16.5 mW with
a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak
jitter with activating the ALGC are 3.7 ps and 32 ps respectively.
- ISSN
- 0018-9200
- Language
- English
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