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VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications

Cited 1 time in Web of Science Cited 1 time in Scopus
Authors
Cho, Jinhyun; Yoon, Sangyong; Park, Sanggyu; Lee, Doowon; Chae, Soo-Ik
Issue Date
2009-01
Publisher
Institute of Electronics, Information and Communication Engineers
Citation
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Vol.E92A, No.1, pp.279-290
Keywords
SMPTE 421M-2006 VC-1design space explorationvideo decodertransaction level modeling
Abstract
In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 90 MHz. We implemented the decoder with a one-poly eight-metal 0.13 mu m CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm(2). In designing, the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HID applications.
ISSN
0916-8508
Language
English
URI
https://hdl.handle.net/10371/80989
DOI
https://doi.org/10.1587/transfun.E92.A.279
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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