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Cache Optimization for H.264/AVC Motion Compensation

Cited 3 time in Web of Science Cited 2 time in Scopus
Authors
Yoon, Sangyong; Chae, Soo-Ik
Issue Date
2008-12
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS; Vol.E91D, No.12, pp.2902-2905
Keywords
cacheDDR SDRAMmemory bandwidthH.264motion compensation
Abstract
In this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the Frame buffer and each line stores in 8 x 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.
ISSN
0916-8532
Language
English
URI
https://hdl.handle.net/10371/80991
DOI
https://doi.org/10.1093/ietisy/e91-d.12.2902
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College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
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