Browse

S-Space College of Engineering/Engineering Practice School (공과대학/대학원) Dept. of Electrical and Computer Engineering (전기·정보공학부) Journal Papers (저널논문_전기·정보공학부)

Fully ion-implanted InP JFET with buried p-layer

Cited 11 time in Web of Science Cited 11 time in Scopus
Export
Authors

Kim, Sung June; Jeong, Jichai; Vella-Coleiro, G.; Smith, P.

Issue Date
1990-01
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
IEEE Electron Device Lett., vol. 11, pp. 57-58, Jan. 1990
Abstract
A buried p-layer has been successfully implemented in a
fully ion implanted InP JFET for the first time. Using Be co-implanted
with Si, a sharp channel profile is obtained. The saturation current has
been reduced and the pinch-off characteristic has been improved with
a slight decrease in transconductance and cutoff frequency. The equhalent
circuits for the JFET with and without the buried p-layer are
compared.
ISSN
0741-3106
Language
English
URI
https://hdl.handle.net/10371/8876
DOI
https://doi.org/10.1109/55.46930
Files in This Item:
Appears in Collections:
College of Engineering/Engineering Practice School (공과대학/대학원)Dept. of Electrical and Computer Engineering (전기·정보공학부)Journal Papers (저널논문_전기·정보공학부)
Show Full Item Record
Find it @ SNU

  • mendeley

Items in S-Space are protected by copyright, with all rights reserved, unless otherwise indicated.

Seoul National University Library, 1 Gwanak-ro, Gwanak-gu, Seoul 08826, Korea TEL: 02-880-5567 Email: s-space@snu.ac.kr youtube

RSS 1.0 RSS 2.0 Atom

Hello

Browse

News About S-Space Seoul National University Library LOGIN