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Showing results 1 to 28 of 28

Issue Date	Title / Author(s) / Citation	File
2014-05	A Wideband Dual-Mode <i>LC</i>-VCO With a Switchable Gate-Biased Active Core Yoon, Heein; Lee, Yongsun; Kim, Jae Joon; Choi, Jaehyouk IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol.61 No.5, pp.289-293	DOI
2014-09	Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol.61 No.9, pp.701-705	DOI
2015-03	A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs Lee, Yongsun; Kim, Mina; Seong, Taeho; Choi, Jaehyouk IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol.62 No.3, pp.635-644	DOI
2016	A PVT-Robust-59-dBc Reference Spur and 450-fsRMS Jitter Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop Lee, Yongsun; Yoon, Heein; Kim, Mina; Choi, Jaehyouk 2016 IEEE SYMPOSIUM ON VLSI CIRCUITS (VLSI-CIRCUITS)
2016-03	A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single <i>LC</i>-VCO for 2G-4G Multistandard Cellular Transceivers Yoon, Heein; Lee, Yongsun; Lim, Younghyun; Tak, Geum-Young; Kim, Hong-Teuk; Ho, Yo-Chuol; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.51 No.3, pp.614-625	DOI
2017	A PVT-Robust-39dBc 1kHz-to-100MHz Integrated-Phase-Noise 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop Using the Averages of Phase Deviations for mm-Band 5G Transceivers Yoo, Seyeon; Choi, Seojin; Kim, Juyeop; Yoon, Heein; Lee, Yongsun; Choi, Jaehyouk 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), pp.324-324
2017	A-242-dB FOM and-71-dBc Reference Spur Ring-VCO-Based Ultra-Low-Jitter Switched-Loop-Filter PLL Using a Fast Phase-Error Correction Technique Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk 2017 SYMPOSIUM ON VLSI CIRCUITS, pp.C186-C187
2017-11	An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Song, Seong-Sik; Kim, Hong-Teuk; Lee, Ockgoo; Choi, Jaehyouk IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol.25 No.11, pp.3006-3018	DOI
2018	153 fS<sub>RMS</sub>-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-<i>LC</i>-Hybrid Injection-Locked Clock Multiplier Choi, Seojin; Yoo, Seyeon; Lee, Yongsun; Jo, Yongwoo; Lee, Jeonghyun; Lim, Younghyun; Choi, Jaehyouk 2018 IEEE SYMPOSIUM ON VLSI CIRCUITS, pp.185-186
2018	Injection-Locked Frequency Multiplier with a Continuous Frequency-Tracking Loop for 5G Transceivers Yoo, Seyeon; Choi, Seojin; Kim, Juyeop; Yoon, Heein; Lee, Yongsun; Choi, Jaehyouk 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.303-304
2018	A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique Lee, Yongsun; Seong, Taeho; Yoo, Seyeon; Choi, Jaehyouk 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.307-308
2018	A-242dB FOM and-75dBc-Reference-Spur Ring-DCO-Based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk 2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC), pp.396-+
2018	A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk ESSCIRC 2018 - IEEE 44TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pp.210-213
2018	A-31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers Yoon, Heein; Kim, Juyeop; Park, Suneui; Lim, Younghyun; Lee, Yongsun; Bang, Jooeun; Lim, Kyoohyun; Choi, Jaehyouk 2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC), pp.366-+
2018-02	A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers Yoo, Seyeon; Choi, Seojin; Kim, Juyeop; Yoon, Heein; Lee, Yongsun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.2, pp.375-388	DOI
2018-04	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique Lee, Yongsun; Seong, Taeho; Yoo, Seyeon; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.4, pp.1192-1202	DOI
2019	A 140fs<sub>rms</sub>-Jitter and-72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk 2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.62, pp.490-+
2019	A 76fs<sub>rms</sub> Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization Kim, Juyeop; Yoon, Heein; Lim, Younghyun; Lee, Yongsun; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.62, pp.258-+
2019-04	An Ultra-Low-Jitter 22.8-GHz Ring-<i>LC</i>-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114 Choi, Seojin; Yoo, Seyeon; Lee, Yongsun; Jo, Yongwoo; Lee, Jeonghyun; Lim, Younghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.4, pp.927-936	DOI
2019-09	A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.9, pp.2501-2512	DOI
2019-12	An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.12, pp.3466-3477	DOI
2019-12	A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single-VCO-Based Edge-Racing Time Quantizer Lee, Jeonghyun; Bang, Jooeun; Lim, Younghyun; Yoo, Seyeon; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk IEEE SOLID-STATE CIRCUITS LETTERS, Vol.2 No.12, pp.305-308	DOI
2020	A-58dBc-Worst-Fractional-Spur and-234dB-FoM<sub>jitter</sub>, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word Seong, Taeho; Lee, Yongsun; Hwang, Chanwoong; Lee, Jeonghyun; Park, Hangi; Lee, Kyuho Jason; Choi, Jaehyouk 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.270-+
2020	A-240dB-FoMjitter and-115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction Lee, Yongsun; Seong, Taeho; Lee, Jeonghyun; Hwang, Chanwoong; Park, Hangi; Choi, Jaehyouk 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.266-+
2021	A 104fs<sub>rms</sub>-Jitter and-61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique Kim, Juyeop; Jo, Yongwoo; Lim, Younghyun; Seong, Taeho; Park, Hangi; Yoo, Seyeon; Lee, Yongsun; Choi, Seojin; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.448-+	DOI
2021	A 365fs<sub>rms</sub>-Jitter and-63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third-Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.442-+	DOI
2021-01	A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.56 No.1, pp.298-309	DOI
2022-09	A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Δ σ M Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.9, pp.2841-2855	DOI