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Issue Date	Title / Author(s) / Citation	File
2019-05	A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation Hyun, Changho; Ko, Hyeongjun; Chae, Joo-Hyung; Park, Hyunkyu; Kim, Suhwan 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), p. 8702456	DOI
2020-06	A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ calibration for Memory Interfaces Jeong, Yong-Un; Park, Hyunkyu; Hyun, Changho; Kim, Suhwan 2020 IEEE SYMPOSIUM ON VLSI CIRCUITS, p. 9162864	DOI
2022-09	A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing Yun, Daeho; Lee, Eonhui; Jung, Woosong; Kim, Kahyun; Beak, Kyung-Min; Kim, Jihee; Lee, Hyun-Bae; Ko, Byeongseon; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3749-3753	DOI
2019-09	A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC Seong, Taeho; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.9, pp.2501-2512	DOI
2018	A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Yoo, Seyeon; Choi, Jaehyouk ESSCIRC 2018 - IEEE 44TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pp.210-213
2021	A 365fs<sub>rms</sub>-Jitter and-63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third-Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.442-+	DOI
2019-06	A 370-fJ/b, 0.0056 mm(2)/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop Ko, Han-Gon; Shin, Soyeong; Kye, Chan-Ho; Lee, Sang-Yoon; Yun, Jaekwang; Jung, Hae-Kang; Lee, Duobock; Kim, Suhwan; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C94-C95	DOI
2021-04	A 3D MODEL-BASED APPROACH FOR FITTING MASKS TO FACES IN THE WILD Hong, Je Hyeong; Kim, Hanjo; Kim, Minsoo; Nam, Gi Pyo; Cho, Junghyun; Ko, Hyeong-Seok; Kim, Ig-Jae Proceedings - International Conference on Image Processing, ICIP, pp.235-239	DOI
2019-06	A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS Park, Kwanseo; Lee, Kwangho; Cho, Sung-Yong; Lee, Jinhyung; Hwang, Jeongho; Choo, Min-Seong; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C194-C195	DOI
2015	A 450-fs Jitter PVT-Robust Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Calibrator with Replica-Delay-Cells Kim, Mina; Choi, Seojin; Choi, Jaehyouk 2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS)
2011	A 45nm SOI-CMOS PLL with a Wideband LC-VCO Lee, Kun-Seok; Beck, Sungho; Jeon, Hamhee; Yoon, Youngchang; Choi, Jaehyouk; Lee, Chang-Ho; Kenney, J. Stevenson 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)
2021-11	A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS Lee, Kwangho; Jung, Woosong; Ju, Haram; Lee, Jinhyung; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2017-02	A 4×32-channel neural recording system for deep brain stimulation systems Kim, Susie; Na, Seung-In; Yang, Youngtae; Kim, Hyunjong; Kim, Taehoon; Cho, Jun Soo; Kim, Jinhyung; Chang, Jin Woo; Kim, Suhwan Journal of Semiconductor Technology and Science, Vol.17 No.1, pp.129-140	view file DOI
2018-06	A 64 Gb/s 1.5 pJ/bit PAM-4 Transmitter with 3-Tap FFE and G(m)-Regulated Active-Feedback Driver in 28 nm CMOS Ju, Haram; Choi, Moon-Chul; Jeong, Gyu-Seob; Jeong, Deog-Kyoon 2018 IEEE SYMPOSIUM ON VLSI CIRCUITS, pp.51-52	DOI
2021-11	A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS Do, Hyungrok; Sull, Jung-Woo; Lee, Seunghyun; Lee, Kwangho; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2022-09	A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector Roh, Seungha; Lee, Kwangho; Shim, Minkyo; Choi, Moon-Chul; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3704-3708	DOI
2019-06	A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS Hwang, Jeongho; Choi, Hong-Seok; Do, Hyungrok; Jeong, Gyu-Seob; Koh, Daehyun; Park, Kwanseo; Kim, Sungwoo; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C268-C269	DOI
2018-07	A 65-nm CMOS 2 x 2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations Lim, Kyoohyun; Lee, Sanghoon; Lee, Yongha; Moon, Byeongmoo; Shin, Hwahyeong; Kang, Kisub; Kim, Seungbeom; Lee, Jinhyeok; Lee, Hyungsuk; Shim, Hyunchul; Sung, Chulhoon; Park, Kumyoung; Lee, Garam; Kim, Minjung; Park, Seokyeong; Jung, Hyosun; Lim, Younghyun; Song, Changhun; Seong, Jaehyeon; Cho, Heechang; Choi, Jaehyouk; Lee, Jongryul; Han, Sangwoo IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.7, pp.1960-1976	DOI
2012	A 65nm CMOS Current Controlled Oscilllator with High Tuning Linearity for Wideband Polar Modulation Tang, Yiwu; Hu, Jianyun; Park, Jongmin; Choi, Jaehyouk; Leung, Lincoln; Narathong, Chiewcharn; Sahota, Kamal 2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)
2019	A 76fs<sub>rms</sub> Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization Kim, Juyeop; Yoon, Heein; Lim, Younghyun; Lee, Yongsun; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.62, pp.258-+

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