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Showing results 1 to 7 of 7

Issue Date	Title / Author(s) / Citation	File	Altmetrics
2019-06	A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS Park, Kwanseo; Lee, Kwangho; Cho, Sung-Yong; Lee, Jinhyung; Hwang, Jeongho; Choo, Min-Seong; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C194-C195	DOI
2019-06	A 0.1 1.62-to-10.8Gb/s Video interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level Lee, Jinhyung; Lee, Kwangho; Kim, Hyojun; Kim, Byungmin; Park, Kwanseo; Jeong, Deog-Kyoon 2019 SYMPOSIUM ON VLSI CIRCUITS, pp.C198-C199
2021-11	A 64 Gb/s 2.09 pJ/b PAM-4 VCSEL Transmitter with Bandwidth Extension Techniques in 40 nm CMOS Do, Hyungrok; Sull, Jung-Woo; Lee, Seunghyun; Lee, Kwangho; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2021-11	A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS Lee, Kwangho; Jung, Woosong; Ju, Haram; Lee, Jinhyung; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2021-11	Y A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS Ju, Haram; Lee, Kwangho; Jung, Woosong; Jeong, Deog-Kyoon IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021)	DOI
2022-06	A 2.5 -32 Gb/s Gen 5-PCIe Receiver with Multi-Rate CDR Engine and Hybrid DFE Choi, Moon-Chul; Lee, Sanghee; Roh, Seungha; Lee, Kwangho; Oh, Jonghyun; Kim, Sungwoo; Kim, Kwandong; Choi, Woo-Seok; Kim, Jaeha; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.6, pp.2677-2681	DOI
2022-09	A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector Roh, Seungha; Lee, Kwangho; Shim, Minkyo; Choi, Moon-Chul; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3704-3708	DOI

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