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Showing results 61 to 89 of 89

Issue Date	Title / Author(s) / Citation	File
2019-12	An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.12, pp.3466-3477	DOI
2020	A-240dB-FoMjitter and-115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction Lee, Yongsun; Seong, Taeho; Lee, Jeonghyun; Hwang, Chanwoong; Park, Hangi; Choi, Jaehyouk 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.266-+
2020	A-58dBc-Worst-Fractional-Spur and-234dB-FoM<sub>jitter</sub>, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word Seong, Taeho; Lee, Yongsun; Hwang, Chanwoong; Lee, Jeonghyun; Park, Hangi; Lee, Kyuho Jason; Choi, Jaehyouk 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.270-+
2020	A 170MHz-Lock-In-Range and-253dB-FoM<sub>jitter</sub>, 12-to-14.5GHz Subsampling PLL with a 150μW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; Choi, Jaehyouk 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.280-+
2020-02	A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method Choi, Se-Eun; Ahn, Hyunjin; Hur, Joonhoi; Kim, Kwan-Woo; Nam, Ilku; Choi, Jaehyouk; Lee, Ockgoo ELECTRONICS, Vol.9 No.2	DOI
2020-12	Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC) Blaauw, David; Lee, Hoi; Keane, John P.; Choi, Jaehyouk; Pamarti, Sudhakar IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.55 No.12, pp.3127-3130	DOI
2021	An 82fs<sub>rms</sub>-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS Yoo, Seyeon; Park, Suneui; Choi, Seojin; Cho, Yoonseo; Yoon, Heein; Hwang, Chanwoong; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.330-+	DOI
2021	A 365fs<sub>rms</sub>-Jitter and-63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third-Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.442-+	DOI
2021	A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency Bang, Jooeun; Choi, Seojin; Yoo, Seyeon; Lee, Jeonghyun; Kim, Juyeop; Choi, Jaehyouk ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pp.351-354	DOI
2021	Session 32 Overview: Frequency Synthesizers Rf Subcommittee Deng, Wei; Choi, Jaehyouk; Wu, Wanghua Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.64, pp.440-441	DOI
2021	A 104fs<sub>rms</sub>-Jitter and-61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique Kim, Juyeop; Jo, Yongwoo; Lim, Younghyun; Seong, Taeho; Park, Hangi; Yoo, Seyeon; Lee, Yongsun; Choi, Seojin; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.448-+	DOI
2021-01	A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.56 No.1, pp.298-309	DOI
2022	A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2022-February, pp.378-380	DOI
2022	A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator Park, Suneui; Yoo, Seyeon; Shin, Yuhwan; Lee, Jeonghyun; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2022-February, pp.212-214	DOI
2022-02	A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.2, pp.480-491	DOI
2022-09	A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Δ σ M Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.9, pp.2841-2855	DOI
2022-09	An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector Park, Suneui; Choi, Seojin; Yoo, Seyeon; Cho, Yoonseo; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.9, pp.2829-2840	DOI
2022-10	A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68 Park, Suneui; Yoo, Seyeon; Shin, Yuhwan; Lee, Jeonghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS	DOI
2022-12	A Low-Jitter Ring-DCO-Based Fractional-<i>N</i> Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.12, pp.3527-3537	DOI
2023	4.6 A 47fs-rms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth Bang, Jooeun; Kim, Jaeho; Jung, Seohee; Park, Suneui; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2023-February, pp.84-86	DOI
2023	A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique Cho, Yoonseo; Lee, Jeonghyun; Park, Suneui; Yoo, Seyeon; Choi, Jaehyouk Digest of Technical Papers - Symposium on VLSI Technology, Vol.2023-June	DOI
2023	A Sub-50-fs RMS Jitter, 103.5-GHz Fundamental-Sampling PLL With an Extended Loop Bandwidth Bang, Jooeun; Jung, Seohee; Kim, Jaeho; Park, Suneui; Choi, Jaehyouk IEEE Solid-State Circuits Letters, Vol.6, pp.201-204	DOI
2023	28.5 A 900μW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces Shin, Yuhwan; Jo, Yongwoo; Kim, Juyeop; Lee, Junseok; Kim, Jongwha; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2023-February, pp.408-410	DOI
2023	A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter Lee, Jeonghyun; Cho, Yoonseo; Kim, Jintae; Choi, Jaehyouk Proceedings of the Custom Integrated Circuits Conference, Vol.2023-April	DOI
2023	A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier Jo, Yongwoo; Kim, Juyeop; Shin, Yuhwan; Hwang, Chanwoong; Park, Hangi; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2023-February, pp.76-78	DOI
2023-12	A Wideband LO Generator for 5G FR1 Bands Using a Single <i>LC</i>-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier Jo, Yongwoo; Kim, Juyeop; Shin, Yuhwan; Park, Hangi; Hwang, Chanwoong; Lim, Younghyun; Choi, Jaehyouk IEEE Journal of Solid-State Circuits, Vol.58 No.12, pp.3338-3350	DOI
2024	10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm Jang, Seheon; Chae, Munjae; Park, Hangi; Hwang, Chanwoong; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.190-192	DOI
2024-02	A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Kim, Juyeop; Jo, Yongwoo; Park, Hangi; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk IEEE Journal of Solid-State Circuits, Vol.59 No.2, pp.424-434	DOI
2024-02	10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique Shin, Yuhwan; Lee, Junseok; Kim, Juyeop; Jo, Yongwoo; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.196-198	DOI

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