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Showing results 1 to 16 of 16

Issue Date	Title / Author(s) / Citation	File	Altmetrics
2017	A PVT-Robust-39dBc 1kHz-to-100MHz Integrated-Phase-Noise 29GHz Injection-Locked Frequency Multiplier with a 600μW Frequency-Tracking Loop Using the Averages of Phase Deviations for mm-Band 5G Transceivers Yoo, Seyeon; Choi, Seojin; Kim, Juyeop; Yoon, Heein; Lee, Yongsun; Choi, Jaehyouk 2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), pp.324-324
2018	Injection-Locked Frequency Multiplier with a Continuous Frequency-Tracking Loop for 5G Transceivers Yoo, Seyeon; Choi, Seojin; Kim, Juyeop; Yoon, Heein; Lee, Yongsun; Choi, Jaehyouk 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), pp.303-304
2018	A-31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers Yoon, Heein; Kim, Juyeop; Park, Suneui; Lim, Younghyun; Lee, Yongsun; Bang, Jooeun; Lim, Kyoohyun; Choi, Jaehyouk 2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC), pp.366-+
2018-02	A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers Yoo, Seyeon; Choi, Seojin; Kim, Juyeop; Yoon, Heein; Lee, Yongsun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.2, pp.375-388	DOI
2019	A 76fs<sub>rms</sub> Jitter and-40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization Kim, Juyeop; Yoon, Heein; Lim, Younghyun; Lee, Yongsun; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.62, pp.258-+
2019-08	A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC Park, Suneui; Kim, Juyeop; Hwang, Chanwoong; Park, Hangi; Yoo, Seyeon; Seong, Taeho; Choi, Jaehyouk IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, Vol.29 No.8, pp.548-550	DOI
2019-12	An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.12, pp.3466-3477	DOI
2020	A 170MHz-Lock-In-Range and-253dB-FoM<sub>jitter</sub>, 12-to-14.5GHz Subsampling PLL with a 150μW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; Choi, Jaehyouk 2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), pp.280-+
2021	A 104fs<sub>rms</sub>-Jitter and-61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique Kim, Juyeop; Jo, Yongwoo; Lim, Younghyun; Seong, Taeho; Park, Hangi; Yoo, Seyeon; Lee, Yongsun; Choi, Seojin; Choi, Jaehyouk 2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), Vol.64, pp.448-+	DOI
2021	A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency Bang, Jooeun; Choi, Seojin; Yoo, Seyeon; Lee, Jeonghyun; Kim, Juyeop; Choi, Jaehyouk ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), pp.351-354	DOI
2022-02	A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.2, pp.480-491	DOI
2023	A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier Jo, Yongwoo; Kim, Juyeop; Shin, Yuhwan; Hwang, Chanwoong; Park, Hangi; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2023-February, pp.76-78	DOI
2023	28.5 A 900μW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces Shin, Yuhwan; Jo, Yongwoo; Kim, Juyeop; Lee, Junseok; Kim, Jongwha; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.2023-February, pp.408-410	DOI
2023-12	A Wideband LO Generator for 5G FR1 Bands Using a Single <i>LC</i>-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier Jo, Yongwoo; Kim, Juyeop; Shin, Yuhwan; Park, Hangi; Hwang, Chanwoong; Lim, Younghyun; Choi, Jaehyouk IEEE Journal of Solid-State Circuits, Vol.58 No.12, pp.3338-3350	DOI
2024-02	A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Kim, Juyeop; Jo, Yongwoo; Park, Hangi; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk IEEE Journal of Solid-State Circuits, Vol.59 No.2, pp.424-434	DOI
2024-02	10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique Shin, Yuhwan; Lee, Junseok; Kim, Juyeop; Jo, Yongwoo; Choi, Jaehyouk Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp.196-198	DOI

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