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Showing results 1 to 18 of 18

Issue Date	Title / Author(s) / Citation	File	Altmetrics
2017-03	Clock buffer polarity assignment under useful skew constraints Joo, Deokjin; Kim, Taewhan Integration, the VLSI Journal, Vol.57, pp.52-61	DOI
2017-04	Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling Kim, Juyeon; Kim, Taewhan IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.36 No.4, pp.641-654	DOI
2017-06	Loosely coupled multi-bit flip-flop allocation for power reduction Moon, Hyoungseok; Kim, Taewhan Integration, the VLSI Journal, Vol.58, pp.125-133	DOI
2019-01	Hybrid asynchronous circuit generation amenable to conventional EDA flow Park, Heechun; Kim, Taewhan Integration, the VLSI Journal, Vol.64, pp.29-39	DOI
2019-08	Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization Jo, Kyeongrok; Ahn, Seyong; Do, Jungho; Song, Taejoong; Kim, Taewhan; Choi, Kyumyung IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.27 No.8, pp.1933-1946	DOI
2019-09	SRAM On-chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage Kim, Taehwan; Jeong, Kwangok; Kim, Taewhan; Choi, Kyumyung 2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019), pp.147-152	DOI
2019-11	Flip-flop State Driven Clock Gating: Concept, Design, and Methodology Hyun, Gyounghwan; Kim, Taewhan 2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), p. 8942061	DOI
2019-11	Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits Hyun, Gyounghwan; Kim, Taewhan 2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), p. 8942064	DOI
2020-03	Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks Ahn, Byungmin; Kim, Taewhan PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020), pp.73-78	DOI
2021	Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis Jo, Kyeongrok; Kim, Taewhan 2021 IEEE 39TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2021), pp.517-524	DOI
2021	Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures Jeong, Jooyeon; Kim, Taewhan 2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), pp.228-231	DOI
2021	Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement Jeong, Eunsol; Park, Heechun; Jeong, Jooyeon; Kim, Taewhan 2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), pp.232-235	DOI
2021-08	Practical Approach to Cell Replacement for Resolving Pin Inaccessibility Kim, Suwan; Kim, Taewhan Midwest Symposium on Circuits and Systems, pp.224-227	DOI
2022-03	A Systematic Removal of Minimum Implant Area Violations under Timing Constraint Jeong, Eunsol; Park, Heechun; Kim, Taewhan Proceedings -Design, Automation and Test in Europe, DATE, pp.933-938	DOI
2022-03	Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model Kim, Suwan; Kim, Taewhan PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), pp.778-783	DOI
2022-06	Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks Kang, Jongsung; Kim, Taewhan Journal of Computing Science and Engineering, Vol.16 No.2, pp.79-87	DOI
2022-06	Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon Heo, Jeongwoo; Jeong, Kwangok; Choi, Jung Yun; Kim, Taewhan; Choi, Kyumyung IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.41 No.6, pp.1929-1942	DOI
2022-09	ECO routing based on network flow method Chung, Sehyeon; Kim, Taewhan Integration, the VLSI Journal, Vol.86, pp.1-8	DOI

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