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Issue Date	Title / Author(s) / Citation	File	Altmetrics
1999	Serial data transfer methods for display-centric IO interconnection 김성준	link
2004	(A)New clock and data recovery using analog dual-tuning LC-VCO 신종신	link
2004	Synchronous mirror delay를 이용한 클럭 발생기의 설계 윤용진	link
2007	Clock generation circuit with all-digital PLL 안현석	link
2009	(A) study on design of all-digital phase-locked loop 오도환	link
2014-02	Synthesis of Low Noise All Digital PLL 김우석	view file
2018-04	A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique Lee, Yongsun; Seong, Taeho; Yoo, Seyeon; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.53 No.4, pp.1192-1202	DOI
2019-12	An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.54 No.12, pp.3466-3477	DOI
2021-01	A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator Yoo, Seyeon; Choi, Seojin; Lee, Yongsun; Seong, Taeho; Lim, Younghyun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.56 No.1, pp.298-309	DOI
2022-02	A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.2, pp.480-491	DOI
2022-06	A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation Kim, Hyojun; Jung, Woosong; Kim, Kwandong; Kim, Sungwoo; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Journal of Solid-State Circuits, Vol.57 No.6, pp.1712-1722	DOI
2022-06	A 2.5 -32 Gb/s Gen 5-PCIe Receiver with Multi-Rate CDR Engine and Hybrid DFE Choi, Moon-Chul; Lee, Sanghee; Roh, Seungha; Lee, Kwangho; Oh, Jonghyun; Kim, Sungwoo; Kim, Kwandong; Choi, Woo-Seok; Kim, Jaeha; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.6, pp.2677-2681	DOI
2022-09	A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Δ σ M Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.9, pp.2841-2855	DOI
2022-09	An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector Park, Suneui; Choi, Seojin; Yoo, Seyeon; Cho, Yoonseo; Choi, Jaehyouk IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.57 No.9, pp.2829-2840	DOI
2023-08	Phase Noise Analysis for Stochastically Injected Oscillators Shin, Jiwon; Choi, Woo-Seok IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.14 No.8, pp.325358-2818	DOI

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