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Issue Date	Title / Author(s) / Citation	File
2012-02	Design Methodology of Clock Networks for TSV Based 3D IC Designs Tak-Yung Kim	link
2016-08	DESIGN METHODOLOGY OF CONTINUOUS TIME ΔΣ MODULATOR FOR WIRELESS COMMUNICATION 나승인	view file
2012-02	Design Methodology of Reliable Clock Networks Based on Adjustable Delay Buffers 임경환	link
2005-05	Design of 2-D Channel Estimation Filters for OFDM Systems Choi, Ji-Woong; Lee, Yong-Hwan ICC 2005. 2005 IEEE International Conference on Communications, vol. 4, pp. 2568-2572, 2005	view file link
2003-07	Design of 2-D MA FIR Filters for Channel Estimation in OFDM Systems Choi, Ji-Woong; Lee, Seung-Woo; Lee, Yong-Hwan 대한전자공학회 하계종합학술대회 논문집, 제26권 제1호, 2003	view file
2021-02	Design of 2D Layered Catalyst by Coherent Heteroepitaxial Conversion for Robust Hydrogen Generation Sim, Yeoseon; Yoon, Aram; Kang, Hee Seong; Kwak, Jinsung; Kim, Se-Yang; Jo, Yongsu; Choe, Daeseong; Na, Woongki; Lee, Min Hee; Park, Soon-Dong; Song, Seunguk; Kim, Daeyong; Yoo, Jung-Woo; Kim, Sung Youb; Cheong, Hyeonsik; Lee, Jae Sung; Lee, Chul-Ho; Lee, Zonghoon; Kwon, Soon-Yong Advanced Functional Materials, Vol.31 No.9, p. 2005449	DOI
2007-05	Design of a Channel-Aware OFDM Transceiver Choi, Ji-Woong; Lee, Yong-Hwan IEEE Trans. Wireless Commun., vol. 6, pp. 1813-1822, 2007	view file DOI
2020	Design of a Controller PHY for High-Capacity DRAM with Pulse-Based Feed-Forward Equalizer 고형준	view file link
2003	Design of a fully-integrated CMOS frequency synthesizer for CDMA applications 구이도	link
2009	Design of a Hybrid Adaptive Decision Feedback Equalizer for High-speed Serial Links 한재덕	link
2017-08	Design of a Low-Power Signal-Specific SAR ADC for ECG Monitoring Applications 임성원	view file
2011-02	Design of a multigigabit/s all-digital clock and data recovery circuit with adaptive proportional gain control 송희수	link
2003-03	Design of a power-line modem for monitoring and control systems Yu, Joonmo; Yu, Hyunseok; Lee, Yong-Hwan ISPLC 2003. International Symposium on Power Line Communications and Its Applications, 2003	view file link
2022	Design of a Quadrature Error Corrector for DQS in HBM3 조서영	view file link
2002-03	Design of a robust modem for power line communications Yu, Hyunseok; Ahn, Eunwoo; Lee, Yong-Hwan ISPLC 2002. International Symposium on Power Line Communications and Its Applications, 2002	view file link
2004	Design of a segment-based OFDM system with opportunistic scheduling 문준	link
2000	Design of a single chip 2.4GHz W-CDMA receiver using multi-phase low frequency conversion technique 이경호	link
2019-08	Design of Adaptive Duty-cycled Protocols in Low-power and Lossy Networks 정승범	view file link
2004	Design of adaptive OFDM wireless transceivers 최지웅	link
2023	Design of ADPLL with Proportional and Integral Gain Co-Optimization Technique 하경준	view file link

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