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Showing results 1 to 58 of 58

Issue Date	Title / Author(s) / Citation	File
2010-11	A 5-Gb/s digitally controlled 3-tap DFE receiver for serial communications Han, Jae Duk; Shin, Woo Yeol; Choi, Woo Seok; Chun, Jung Hoon; Kim, Su Hwan; Jeong, Deog Kyoon 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp.85-88	DOI
2011-11	250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 mu m CMOS Lee, Sang-Yoon; Lee, Hyung-Rok; Kwak, Young-Ho; Choi, Woo Seok; Yoo, Byoung-Joo; Shim, Daeyun; Kim, Chulwoo; Jeong, Deog-Kyoon IEEE Journal of Solid-State Circuits, Vol.46 No.11, pp.2560-2570	DOI
2012-09	A Digital Readout IC with Digital Offset Canceller for Capacitive Sensors Lim, Dong-Hyuk; Lee, Sang-Yoon; Choi, Woo Seok; Park, Jun-Eun; Jeong, Deog-Kyoon JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.12 No.3, pp.278-285	DOI
2013-06	A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR Shu, Guanghua; Saxena, Saurabh; Choi, Woo-Seok; Talegaonkar, Mrumnay; Inti, Rajesh; Elshazly, Amr; Young, Brian; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6578694
2013-06	A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering Choi, Woo Seok; Anand, Tejasvi; Shu, Guanghua; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C280-C281
2014-02	8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS Shu, Guanghua; Choi, Woo-Seok; Saxena, Saurabh; Anand, Tejasvi; Elshazly, Amr; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.57, pp.150-151	DOI
2014-04	A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop Shu, Guanghua; Saxena, Saurabh; Choi, Woo Seok; Talegaonkar, Mrunmay; Inti, Rajesh; Elshazly, Amr; Young, Brian; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.49 No.4, pp.1036-1047	DOI
2014-06	A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo-Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858446	DOI
2014-06	A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with-106dBc/Hz In-band noise using time amplifier based TDC Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858391	DOI
2014-06	A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter Talegaonkar, M.; Anand, T.; Elkholy, A.; Elshazly, A.; Nandwana, R.K.; Saxena, S.; Young, B.; Choi, Woo Seok; Hanumolu, P.K. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, p. 6858392	DOI
2015-02	A 0.45-to-0.7V 1-to-6Gb/s 0.29-to-0.58pJ/b Source-Synchronous Transceiver Using Automatic Phase Calibration in 65nm CMOS Choi, Woo Seok; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.58, pp.66-67	DOI
2015-03	A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links Choi, Woo Seok; Anand, Tejasvi; Shu, Guanghua; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.50 No.3, pp.737-748	DOI
2015-04	A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.882-895	DOI
2015-04	A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.50 No.4, pp.867-881	DOI
2015-08	A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS Saxena, Saurabh; Shu, Guanghua; Nandwana, Romesh Kumar; Talegaonkar, Mrunmay; Elkholy, Ahmed; Anand, Tejasvi; Kim, Seong Joong; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C352-C353	DOI
2016-02	A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Talegaonkar, Mrunmay; Anand, Tejasvi; Elkholy, Ahmed; Elshazly, Amr; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.51 No.2, pp.428-439	DOI
2016-02	A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b Source Synchronous Transceiver Using DVFS and Rapid On/Off in 65nm CMOS Shu, Guanghua; Choi, Woo Seok; Saxena, Saurabh; Kim, Seong-Joong; Talegaonkar, Mrunmay; Nandwana, Romesh; Elkholy, Ahmed; Wei, Da; Nandi, Timir; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.59, pp.398-U558
2016-10	Digital Clock and Data Recovery Circuits for Optical Links Shu, Guanghua; Choi, Woo Seok; Hanumolu, Pavan Kumar Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC, pp.126-129	DOI
2017-02	A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm CMOS Nandwana, Romesh Kumar; Saxena, Saurabh; Elkholy, Ahmed; Talegaonkar, Mrunmay; Zhu, Junheng; Choi, Woo Seok; Elmallah, Ahmed; Hanumolu, Pavan Kumar Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.60, pp.492-493	DOI
2017-05	A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver Saxena, Saurabh; Shu, Guanghua; Nandwana, Romesh Kumar; Talegaonkar, Mrunmay; Elkholy, Ahmed; Anand, Tejasvi; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.52 No.5, pp.1399-1411	DOI
2017-05	A 10MHz 2mA-800mA 0.5V-1.5V 90% Peak Efficiency Time-Based Buck Converter with Seamless Transition between PWM/PFM Modes Kim, Seong Joong; Choi, Woo Seok; Pilawa-Podgurski, Robert; Hanumolu, Pavan Kumar Proceedings of the Custom Integrated Circuits Conference, p. 7993619	DOI
2017-05	A 45-75MHz 197-452μW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS Zhu, Junheng; Mahalley, Makrand; Shu, Guanghua; Choi, Woo Seok; Nandwana, Romesh Kumar; Elkholy, Ahmed; Sahoo, Bibhudatta; Hanumolu, Pavan Kumar Proceedings of the Custom Integrated Circuits Conference, Vol.2017-April, p. 7993679	DOI
2017-09	A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS Talegaonkar, Mrunmay; Anand, Tejasvi; Elkholy, Ahmed; Elshazly, Amr; Nandwana, Romesh Kumar; Saxena, Saurabh; Young, Brian; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.52 No.9, pp.2306-2320	DOI
2018-03	A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes Kim, Seong Joong; Choi, Woo Seok; Pilawa-Podgurski, Robert; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.53 No.3, pp.814-824	DOI
2018-03	A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation Choi, Woo Seok; Shu, Guanghua; Talegaonkar, Mrunmay; Liu, Yubo; Wei, Da; Benini, Luca; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.53 No.3, pp.884-895	DOI
2018-04	A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS Elmallah, Ahmed; Ahmed, Mostafa Gamal; Elkholy, Ahmed; Choi, Woo Seok; Hanumolu, Pavan Kumar 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, pp.1-4	DOI
2018-05	A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR Kim, Dongwook; Choi, Woo Seok; Elkholy, Ahmed; Kenney, Jack; Hanumolu, Pavan Kumar 2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), pp.1-4
2018-06	Guaranteeing Local Differential Privacy on Ultra-low-power Systems Choi, Woo Seok; Tomei, Matthew; Vicarte, Jose Rodrigo Sanchez; Hanumolu, Pavan Kumar; Kumar, Rakesh Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA, pp.561-574	DOI
2019-03	A 15-Gb/s Sub-Baud-Rate Digital CDR Kim, Dongwook; Choi, Woo Seok; Elkholy, Ahmed; Kenney, Jack; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.54 No.3, pp.685-695	DOI
2019-08	A 0.016 mm<SUP>2</SUP> 0.26-μW/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS Zhu, Junheng; Choi, Woo Seok; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.54 No.8, pp.2186-2194	DOI
2020-08	A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS Kim, Dongwook; Ahmed, Mostafa G.; Choi, Woo-Seok; Elkholy, Ahmed; Hanumolu, Pavan Kumar IEEE Journal of Solid-State Circuits, Vol.55 No.8, pp.2196-2205	DOI
2021-02	Cheetah: Optimizing and Accelerating Homomorphic Encryption for Private Inference Reagen, Brandon; Choi, Woo-Seok; Ko, Yeongil; Lee, Vincent T.; Lee, Hsien-Hsin S.; Wei, Gu-Yeon; Brooks, David IEEE High-Performance Computer Architecture Symposium Proceedings, Vol.2021-February, pp.26-39	DOI
2021-09	0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link Lee, Woonghee; Shim, Minkyo; Lee, Yunhee; Yang, Heejin; Ko, Han-Gon; Choi, Woo-Seok; Jeong, Deog-Kyoon European Solid-State Circuits Conference, pp.475-478	DOI
2022-04	Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link Lee, Woonghee; Shim, Minkyo; Lee, Yunhee; Yang, Heejin; Shin, Soyeong; Choi, Woo Seok; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.4, pp.2056-2060	DOI
2022-05	A Multimodal Approach to Huge Fibrous Dysplasia With Ocular Symptoms Using a Navigation System and Endoscope Cho, Seung Woo; Choi, Woo Seok; Kim, Baek-Kyu Journal of Craniofacial Surgery, Vol.33 No.3, pp.E342-E345	DOI
2022-06	A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation Kim, Hyojun; Jung, Woosong; Kim, Kwandong; Kim, Sungwoo; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Journal of Solid-State Circuits, Vol.57 No.6, pp.1712-1722	DOI
2022-06	A 2.5 -32 Gb/s Gen 5-PCIe Receiver with Multi-Rate CDR Engine and Hybrid DFE Choi, Moon-Chul; Lee, Sanghee; Roh, Seungha; Lee, Kwangho; Oh, Jonghyun; Kim, Sungwoo; Kim, Kwandong; Choi, Woo-Seok; Kim, Jaeha; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.6, pp.2677-2681	DOI
2022-06	0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link Lee, YunHee; Lee, Woong Hee; Shim, Min Kyo; Shin, So Yeong; Choi, Woo Seok; Jeong, Deog Kyoon Digest of Technical Papers - Symposium on VLSI Technology, Vol.2022-June, pp.30-31	DOI
2022-06	Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons Song, Joonghyun; Shin, Jiwon; Kim, Hanseok; Choi, Woo Seok 2022 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2022): INTELLIGENT TECHNOLOGY IN THE POST-PANDEMIC ERA, pp.5-8	DOI
2022-06	Improving Spiking Neural Network Accuracy Using Time-based Neurons Kim, Hanseok; Choi, Woo-Seok IEEE International Symposium on Circuits and Systems proceedings, Vol.2022-May, pp.2162-2166	DOI
2022-07	A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns Hwang, Young-Ha; Oh, Jonghyun; Choi, Woo Seok; Jeong, Deog Kyoon; Park, Jun-Eun IEEE Journal of Solid-State Circuits, Vol.57 No.7, pp.2236-2249	DOI
2022-09	A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing Yun, Daeho; Lee, Eonhui; Jung, Woosong; Kim, Kahyun; Beak, Kyung-Min; Kim, Jihee; Lee, Hyun-Bae; Ko, Byeongseon; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.69 No.9, pp.3749-3753	DOI
2022-10	Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital Converter Ahn, Honggyoo; Song, Joonghyun; Choi, Woo Seok International SoC Design Conference, ISOCC, pp.141-142	DOI
2022-10	A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion Song, Joonghyun; Choi, Woo-Seok International SoC Design Conference, ISOCC, pp.398-399	DOI
2022-10	Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching Pursuit Park, Hyunjun; Choi, Woo Seok International SoC Design Conference, ISOCC, pp.123-124	DOI
2022-10	Impact of Oscillator Phase Noise on Time-Domain SNN Performance Park, Jia; Choi, Woo-Seok International SoC Design Conference, ISOCC, pp.364-365	DOI
2023-04	Fast Performance Evaluation Methodology for High-speed Memory Interfaces Kim, Taehoon; Lee, Yoona; Choi, Woo Seok Proceedings -Design, Automation and Test in Europe, DATE, p. 189131	DOI
2023-05	A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation Kim, Kahyun; Yun, Daeho; Baek, Kyungmin; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE International Symposium on Circuits and Systems proceedings, Vol.2023-May, p. 190917	DOI
2023-08	Phase Noise Analysis for Stochastically Injected Oscillators Shin, Jiwon; Choi, Woo-Seok IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.14 No.8, pp.325358-2818	DOI
2023-09	A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving-64 dBc Reference-Spur and-239 dB FoM Shin, Jiwon; Song, Joonghyun; Kim, Jihee; Choi, Woo-Seok European Solid-State Circuits Conference, Vol.2023-September, pp.273-276	DOI
2023-09	A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-Low-Power Always-On Event Detection Roh, Hyeri; Choi, Woo Seok IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.70 No.9, pp.3719-3723	DOI
2023-10	A Baud-Rate Clock and Data Recovery With Collaborative Maximum-Eye Tracking Method Kim, Jihee; Choi, Woo Seok 2023 20th International SoC Design Conference, ISOCC, pp.113-114	DOI
2023-10	A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors Song, Jeongeun; Lee, Sunyoung; Shin, Minseok; Kwon, Ohjun; Kim, Hansang; Park, Yujin; Hwang, Gyubeom; Jung, Hyekyoung; Jeong, Hoesam; Song, Changrock; Choi, Woo Seok 2023 20th International SoC Design Conference, ISOCC, pp.31-32	DOI
2023-10	Performance Comparison of Clocked Comparators Using Impulse Sensitivity Function Kim, Taehoon; Choi, Woo Seok 2023 20th International SoC Design Conference, ISOCC, pp.337-338	DOI
2023-10	Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis Roh, Hyeri; Choi, Woo Seok 2023 20th International SoC Design Conference, ISOCC, pp.351-352	DOI
2023-10	An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism Park, Jia; Choi, Woo Seok 2023 20th International SoC Design Conference, ISOCC, pp.265-266	DOI
2023-11	A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift Lee, Kwang-Hoon; Park, Jung-Hun; Lee, Yongjae; Song, Yeonggeun; Roh, Seungha; Shim, Minkyo; Song, Yoonho; Jung, Woosong; Hwang, Young-Ha; Oh, Jonghyun; Choi, Woo-Seok; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.70 No.11, pp.4003-4007	DOI
2023-11	A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge Yun, Daeho; Park, Minsu; Kim, Kahyun; Baek, Kyungmin; Lee, Eonhui; Choi, Woo Seok; Jeong, Deog-Kyoon 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, p. 195637	DOI