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Showing results 1 to 60 of 79

Issue Date	Title / Author(s) / Citation	File
2012-05	Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs) Lee, Gibong; Choi, Woo Young Ieice Transactions on Electronics, Vol.E95.C No.5, pp.910-913	DOI
2012-06	Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors Lee, Jae Sung; Choi, Woo Young; Kang, In Man Japanese Journal of Applied Physics, Vol.51 No.6S, p. 06FE03	DOI
2012-10	Effects of Device Geometry on Hetero-Gate-Dielectric Tunneling Field-Effect Transistors Lee, Min Jin; Choi, Woo Young IEEE Electron Device Letters, Vol.33 No.10, pp.1459-1461	DOI
2013-03	Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors Lee, Gibong; Jang, Jung-Shik; Choi, Woo Young Semiconductor Science and Technology, Vol.28 No.5, p. 052001	DOI
2013-05	Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory Choi, Woo Young; Han, Min Su; Han, Boram; Seo, Dongsun; Cho, Il Hwan IEICE Transactions on Electronics, Vol.E96.C No.5, pp.714-717	DOI
2013-08	Development of sacrificial layer wet etch process of TiNi for nano-electro-mechanical device application Park, Byung Kyu; Choi, Woo Young; Cho, Eou Sik; Cho, Il Hwan JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.13 No.4, pp.410-414	DOI
2013-08	Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs) Choi, Kyoung Min; Choi, Woo Young IEEE Electron Device Letters, Vol.34 No.8, pp.942-944	DOI
2013-12	Linearity of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors Lee, Hyun Kook; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.13 No.6, pp.551-555	DOI
2014-01	Dual random circuit breaker network model with equivalent thermal circuit network Kim, Kwanyong; Yoon, Seong Jun; Choi, Woo Young Applied Physics Express, Vol.7 No.2, p. 024203	DOI
2014-03	Effects of abnormal cell-to-cell interference on p-type floating gate and control gate NAND flash memory Kim, Yong Jun; Kang, Jun Geun; Lee, Byungin; Cho, Gyu-Seog; Park, Sung-Kye; Choi, Woo Young Japanese Journal of Applied Physics, Vol.53 No.4S, p. 04ED12	DOI
2014-06	A Finite Element Model for Bipolar Resistive Random Access Memory Kim, Kwanyong; Lee, Kwangseok; Lee, Keun-Ho; Park, Young-Kwan; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.14 No.3, pp.268-273	DOI
2014-10	On-State Resistance Instability of Programmed Antifuse Cells during Read Operation Han, Jae Hwan; Lee, Hyunjin; Kim, Wansoo; Yoon, Gyuhan; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.14 No.5, pp.503-507	DOI
2014-10	Fringe Field Effects on Transient Characteristics of Nano-Electromechanical (NEM) Nonvolatile Memory Cells Han, Boram; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.14 No.5, pp.609-614	DOI
2014-11	Disturbance characteristics of charge trap flash memory with tunneling field-effect transistor Xi, Ning; Cho, Eou-Sik; Choi, Woo Young; Choi, Il Hwan Japanese Journal of Applied Physics, Vol.53 No.11, p. 114201	DOI
2014-11	Influence of Fringe Field on Nano-Electromechanical (NEM) Memory Cells Han, Boram; Song, Ji Yong; Choi, Woo Young IEEE Transactions on Nanotechnology, Vol.13 No.6, pp.1102-1106	DOI
2014-12	Scale Effects on Stiction-Induced Release Voltage Shift of Nano-Electromechanical (NEM) Memory Cells Han, Jae Hwan; Song, Jiyong; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.14 No.12, pp.9589-9593	DOI
2014-12	Fabrication and Electrical Characterization of Graphene Formed Chemically on Nickel Nano Electro Mechanical System (NEMS) Switch Choe, Byeong-In; Lee, Jung-Kyu; Lee, Bora; Kim, Kwanyong; Choi, Woo Young; Hong, Byung Hee; Lee, Jong-Ho Journal of Nanoscience and Nanotechnology, Vol.14 No.12, pp.9418-9424	DOI
2015-02	Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays Kim, Yong Jun; Choi, Woo Young IEEE Transactions on Electron Devices, Vol.62 No.2, pp.673-679	DOI
2015-03	Germanium electron-hole bilayer tunnel field-effect transistors with a symmetrically arranged double gate Jeong, Woo Jin; Kim, Tae Kyun; Moon, Jung Min; Park, Min Gyu; Yoon, Young Gwang; Hwang, Byeong Woon; Choi, Woo Young; Shin, Mincheol; Lee, Seok-Hee Semiconductor Science and Technology, Vol.30 No.3, p. 035021	DOI
2015-04	Influence of Preferred Gate Metal Grain Orientation on Tunneling FETs Choi, Kyoung Min; Lee, Won-Sok; Lee, Keun-Ho; Park, Young-Kwan; Choi, Woo Young IEEE Transactions on Electron Devices, Vol.62 No.4, pp.1353-1356	DOI
2015-06	Negative Capacitance in Organic/Ferroelectric Capacitor to Implement Steep Switching MOS Devices Jo, Jaesung; Choi, Woo Young; Park, Jung-Dong; Shim, Jae Won; Yu, Hyun-Yong; Shin, Changhwan Nano Letters, Vol.15 No.7, pp.4553-4556	DOI
2015-09	Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical Hybrid Reconfigurable Circuits Choi, Woo Young; Kim, Yong Jun IEEE Electron Device Letters, Vol.36 No.9, pp.887-889	DOI
2016-02	Impact of gate dielectric constant variation on tunnel field-effect transistors (TFETs) Kim, Seung Kyu; Choi, Woo Young Solid-State Electronics, Vol.116, pp.88-94	DOI
2016-04	Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation Huh, In; Cheon, Woo Young; Choi, Woo Young Applied Physics Letters, Vol.108 No.15, p. 153506	DOI
2016-05	Influence of Number Fluctuation and Position Variation of Channel Dopants and Gate Metal Grains on Tunneling Field-Effect Transistors (TFETs) Choi, Kyoung Min; Kim, Seung Kyu; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.16 No.5, pp.5255-5258	DOI
2016-05	Multi-Bit Nano-Electromechanical Nonvolatile Memory Cells (Zigzag T Cells) for the Suppression of Bit-to-Bit Interference Choi, Woo Young; Han, Jae Hwan; Cha, Tae Min Journal of Nanoscience and Nanotechnology, Vol.16 No.5, pp.5164-5167	DOI
2016-06	Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) Choi, Woo Young; Lee, Hyun Kook Nano Convergence, Vol.3, p. 13	DOI
2016-06	Hump Effects of Germanium/Silicon Heterojunction Tunnel Field-Effect Transistors Kim, Sang Wan; Choi, Woo Young IEEE Transactions on Electron Devices, Vol.63 No.6, pp.2583-2588	DOI
2016-10	Influence of the Source Doping Concentration on the Subthreshold Swing (S) of Tunneling Field-Effect Transistors (TFETs) Huh, In; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.16 No.10, pp.10241-10246	DOI
2016-10	Influence of Electron and Hole Distribution on 2T SONOS Embedded NVM Choi, Woo Young; Kim, Da Som; Lee, Tae Ho; Kwon, Young Jun; Park, Sung-Kun; Yoon, Gyuhan JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.16 No.5, pp.624-629	DOI
2016-10	Esaki-Tunneling-Assisted Tunnel Field-Effect Transistors for Sub-0.7-V Operation Park, Jong Han; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.16 No.10, pp.10237-10240	DOI
2016-10	Random Telegraph Noise Model of Tunnel Field-Effect Transistors Lee, Jang Woo; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.16 No.10, pp.10264-10267	DOI
2017-01	A sub-0.5 V operating RF low noise amplifier using tunneling-FET Jhon, Hee-Sauk; Jeon, Jongwook; Kang, Myunggon; Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.2, p. 020303	DOI
2017-01	Effects of drain bias on the statistical variation of double-gate tunnel field-effect transistors Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD01	DOI
2017-02	Influence of Intercell Trapped Charge on Vertical NAND Flash Memory Choi, Woo Young; Kwon, Hyug Su; Kim, Yong Jun; Lee, Byungin; Yoo, Hyunseung; Choi, Sangmoo; Cho, Gyu-Seog; Park, Sung-Kye IEEE Electron Device Letters, Vol.38 No.2, pp.164-167	DOI
2017-02	Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot- carrier Stress Bias Conditions Lim, In Eui; Jhon, Heesauk; Yoon, Gyuhan; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.17 No.1, pp.94-100	DOI
2017-02	Influence of line-edge roughness on multiple-gate tunnel field-effect transistors Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD06	DOI
2017-03	Monolithic three-dimensional tunnel FET-nanoelectromechanical hybrid reconfigurable logic circuits Kim, Seung Kyu; Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.4S, p. 04CD12	DOI
2017-04	Mutually-Actuated-Nano-Electromechanical (MANEM) Memory Switches for Scalability Improvement Lee, Ho Moon; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.17 No.2, pp.199-203	DOI
2017-04	Triple-gate Tunnel FETs Encapsulated with an Epitaxial Layer for High Current Drivability Lee, Jang Woo; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.17 No.2, pp.271-276	DOI
2017-07	Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field Kim, Sangwan; Choi, Woo Young Japanese Journal of Applied Physics, Vol.56 No.8, p. 084301	DOI
2017-08	An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs Huh, In; Park, Sangchun; Shin, Mincheol; Choi, Woo Young IEEE Transactions on Electron Devices, Vol.64 No.8, pp.3502-3507	DOI
2017-09	Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation Kwon, Hyug Su; Kim, Seung Kyu; Choi, Woo Young IEEE Electron Device Letters, Vol.38 No.9, pp.1317-1320	DOI
2017-10	Nanoelectromechanical Nonvolatile Memory Cells with Scaled Beam Dimensions Choi, Woo Young Journal of Nanoelectronics and Optoelectronics, Vol.12 No.10, pp.1134-1136	DOI
2017-12	Lateral Nanoelectromechanical Relays for Reconfigurable Logic Choi, Woo Young; Kwon, Hyuck-In; Kim, Kwanyong Journal of Nanoelectronics and Optoelectronics, Vol.12 No.12, pp.1402-1405	DOI
2018-04	On-current Modeling of 70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions Choi, Woo Young; Lim, In Eui; Jhon, Heesauk; Yoon, Gyuhan JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.18 No.2, pp.131-138	DOI
2018-06	Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS-NEM Hybrid Circuits Jo, Hyun Chan; Choi, Woo Young Micromachines, Vol.9 No.7, p. 317	DOI
2018-09	Compact Potential Model for Si1-xGex/Si Heterojunction Double-Gate Tunnel Field-Effect Transistors (TFETs) Kim, Sangwan; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.18 No.9, pp.5953-5958	DOI
2018-09	Switching Voltage Analysis of Nanoelectromechanical Memory Switches for Monolithic 3-D CMOS-NEM Hybrid Reconfigurable Logic Circuits Lee, Ho Moon; Jo, Hyun Chan; Kwon, Hyug Su; Choi, Woo Young IEEE Transactions on Electron Devices, Vol.65 No.9, pp.3780-3785	DOI
2019-04	Influence of Etch Profiles on the Leakage Current and Capacitance of 3-D DRAM Storage Capacitors Shin, Seongun; Yoon, Gyuhan; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.19 No.2, pp.208-213	DOI
2019-04	Selection Line Optimization of Nanoelectromechanical (NEM) Memory Switches for Stress Relief Jo, Hyun Chan; Kang, Min Hee; Choi, Woo Young JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, Vol.19 No.2, pp.203-207	DOI
2019-04	A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors Choi, Woo Young; Yoon, Gyuhan; Chung, Woo Young; Cho, Younghoon; Shin, Seongun; Ahn, Kwang Ho Micromachines, Vol.10 No.4, p. 256	DOI
2019-04	Slingshot Pull-In Operation for Low-Voltage Nanoelectromechanical Memory Switches Choi, Woo Young; Kwon, Hyug Su IEEE Transactions on Electron Devices, Vol.66 No.4, pp.2040-2043	DOI
2019-10	Active Region Formation of Nanoelectromechanical (NEM) Devices for Complementary-Metal-Oxide-Semiconductor-NEM Co-Integration Cha, Tae Min; Jo, Hyun Chan; Kwon, Hyug Su; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.19 No.10, pp.6123-6127	DOI
2020-01	Design guideline of tunnel field-effect transistors (TFETs) considering negative differential transconductance (NDT) Lee, Jang Woo; Choi, Woo Young Solid-State Electronics, Vol.163, p. 107659	DOI
2020-04	Dynamic Slingshot Operation for Low-Operation-Voltage Nanoelectromechanical (NEM) Memory Switches Kang, Min Hee; Choi, Woo Young IEEE Access, Vol.8, pp.65683-65688	DOI
2020-04	Design Guidelines for Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs) Lee, Jang Woo; Choi, Woo Young IEEE Access, Vol.8, pp.67617-67624	DOI
2020-05	Physically Consistent Method for Calculating Trap-Assisted-Tunneling Current Applied to Line Tunneling Field-Effect Transistor Najam, Faraz; Kim, Sangwan; Choi, Woo Young; Yu, Yun Seop IEEE Transactions on Electron Devices, Vol.67 No.5, pp.2106-2112	DOI
2020-05	Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage Choi, Woo Young Micromachines, Vol.11 No.6, p. 543	DOI
2020-07	Notched Anchor Design for Low Voltage Operation of Nanoelectromechanical (NEM) Memory Switches Kang, Min-Hee; Jo, Hyun-Chan; Choi, Woo Young Journal of Nanoscience and Nanotechnology, Vol.20 No.7, pp.4198-4202	DOI

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