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Showing results 61 to 120 of 142

Issue Date	Title / Author(s) / Citation	File
2009	Design of fully integrated CMOS 40-Gbs serial link transceiver 김정겸	link
2009	(A) high-accuracy clock synchronization system over packet switched networks 한지호	link
2009	(A) study on the design of wide range CDR without a external reference clock 황문상	link
2009	(A) study on design of all-digital phase-locked loop 오도환	link
2009-06	A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification Kim, Young-Deok; Ahn, Hyun-Seok; Kim, Suhwan; Jeong, Deog-Kyoon IEEE Transactions on Circuits and Systems Part 1 Regular Papers, vol. 56, no. 6, pp. 1221-1230	view file DOI
2009-08	High-Speed 10-bit LCD Column Driver with a Split DAC and a Class-AB Output Buffer Woo, Jong-Kwan; Shin, Dong-yong; Jeong, Deog-Kyoon; Kim, Suhwan IEEE Transactions on Consumer Electronics, vol. 55, no. 3, pp. 1431-1438	view file DOI
2009-11	A 1.35GHz All-Digital Fractional-N PLL with Adaptive Loop Gain Controller and Fractional Divider Kim, Deok-Soo; Song, Heesoo; Kim, Taeho; Kim, Suhwan; Jeong, Deog-Kyoon IEEE Asian Solid-State Circuits Conference, November 16-18, 2009 / Taipei, Taiwan, pp. 161-164	view file
2010	듀티사이클 변화에 둔감한 지연동기루프의 설계 장성천	link
2010	10 Gbs 급 CMOS 광 수신기 전단회로의 설계 및 구현 박규상	link
2010-03	High-resolution time-to-digital converter utilising fractional difference conversion scheme Xing, Nan; Shin, W.-Y.; Jeong, K.-K.; Kim, Suhwan Electronics Letters- IEE (2010),46(6):398	DOI
2010-11	A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller Kim, Deok-Soo; Song, Heesoo; Kim, Taeho; Kim, Suhwan; Jeong, Deog-Kyoon IEEE Journal of Solid State Circuits, vol.45, no.11, pp. 2300-2311	DOI
2010-11	A 5-Gb/s Digitally Controlled 3-Tap DFE Receiver for Serial Communications Han, Jae-Duk; Shin, Woo-Yeol; Choi, Woo-Seok; Chun, Jung-Hoon; Kim, Suhwan; Jeong, Deog-Kyoon IEEE Asian Solid-State Circuits Conference, November 8-10, 2010, Beijing, China	view file
2011-02	(A) study on clock generation circuit using multiphase delay-locked-loop 송호영	link
2011-02	Design of all-digital PLL using adaptive loop gain controller 김덕수	link
2011-02	(A) multidrop bus design scheme with resistor-based impedance matching on nonuniform impedance lines 윤여환	link
2011-02	Design of a multigigabit/s all-digital clock and data recovery circuit with adaptive proportional gain control 송희수	link
2011-02	PVT 변화에 둔감한 DCO를 이용한 ADPLL 설계 김성우	link
2011-08	Design of low-power digital-readout interface for capacitive microphones 이상윤	link
2012-02	3.6/5.2GHz 듀얼 밴드를 갖는 All-Digital Fractional-N Phase-Locked Loop의 설계 임정필	link
2012-02	0.13μm CMOS 공정을 이용한 12.5Gb/s 광 수신기 및 광 변조기 드라이버 구현 김동욱	link
2012-02	Switched - Capacitor Converter를 이용한 LED driver의 구현 김혜원	link
2013-02	(A) study on multichannel receivers with enhanced lane expandability and loop linearity 유병주	view file
2013-08	(A) design of 20Gbps/Lane serial link for memory interface 지한규	view file
2013-08	2배 시간증폭기와 버니어 링 구조의 TDC를 이용한 All-Digital PLL 천유상	view file
2014-02	Synthesis of Low Noise All Digital PLL 김우석	view file
2014-08	Design of DisplayPort Receiver with Video Clock Frequency Error Compensation Scheme Taeho Kim	view file
2015-02	65nm CMOS 공정을 이용한 광 변조기 드라이버 구현 김윤수	view file
2015-08	Design of All-Digital PLL Using Statistical Data of Bang-Bang Phase Detection 장성천	view file
2016-08	An AC-DC LED Driver with a Two Parallel Floating Buck Topology for Reducing the Light Flicker in Lighting Applications to Low-Risk Levels 김현창	view file
2016-08	Circuit Techniques for Low-Power, Area-Efficient Wireline Transceivers 배우람	view file
2016-08	Design of High-Speed Optical Receiver with All-Digital Clock and Data Recovery 추상혁	view file
2017-02	Design and Fabrication of Highly Stable Oxide TFT Shift-Register Employing the Current Sensing Feedback System 유봉현	view file
2017-02	Design of Injection-Locked PLL with Digital Calibration of Frequency Error and Path Mismatch 김성우	view file
2017-02	Design of Analog Front-End of Touch-Screen Controller with Enhanced Noise Immunity and Configurable SNR and Frame Rate 박준은	view file
2017-08	Design of High-Speed CMOS Interface Circuits for Optical Communications 정규섭	view file
2018-08	Design and Analysis of Low Dropout Regulator using Ground Regulation Technique 박성호	view file
2019-02	다이렉트 경로를 이용한 5/8GHz 듀얼 모드 All-Digital Phase-Locked Loop의 설계 김병민	view file
2019-02	Design of Injection-Locked PLL and CDR with Circuit Techniques for Optimum Operation 추민성	view file
2019-02	A Study on Subharmonically Injection-Locked PLL With Dual-Edge Complementary Switched Injection 조성용	view file
2019-08	A Study on Low-Power, High-Speed PAM-4 Transmitter with Current-Driven Feedback Driver 주하람	view file link
2019-08	Design of Low Power Analog Front-End of Touch-Screen Controller With Adiabatic Signal Generation and Optimized Sensor Modes 박지헌	view file link
2019-08	Design of Analog Front-End for Low-Power Touchscreen Controller and Circuit Techniques for Low-Power, High-Resolution Analog-to-Digital Converters 황영하	view file link
2019-08	Design of High-Speed Receiver for Video Interface with Adaptive Equalization 이진형	view file link
2019-08	Design of High-Speed Power-Efficient Optical Transmitter With Push-Pull Driving Technique 황정호	view file link
2019-08	Design of Wide-Range Clock and Data Recovery with Multi-Phase Oversampling Frequency Detection 박관서	view file link
2020	Quadrature Resonant Clock with Frequency Tuning Capacitor and Amplitude Control Feedback Loop 윤창수	view file link
2020	Design of High-Density Power-Efficient Transceiver for Next-Generation HBM 고한곤	view file link
2021	시간 기반 등화기를 포함한 고속 저전력 송신기의 설계 계찬호	view file link
2021-02	Design of Voltage and Temperature-tolerant Clock Path and Phase Error Corrector for High-Speed DRAM Interface 신소영	view file link
2021-02	Design of Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation 주혜윤	view file link
2021-02	Design and Analysis of All-Digital Phase-Locked Loop for Automotive CIS Interface 양희진	view file link
2021-02	Design of Offset-Canceling Sense Amplifier for DRAM and Analysis on Offset-Canceling Methods 윤정민	view file link
2022	Design of Asymmetric Simultaneous Bidirectional Transceivers for Next-Generation Automotive Camera Link 이웅희	view file link
2022	Design of High-Speed Power-Efficient Transmitter Systems with Bandwidth Extension Techniques 도형록	view file link
2022	Design of Phase Locked-Loop with Switched Capacitor Loop Filter and Source Switched Charge Pump 이용재	view file link
2022	Design of High-Speed Transmitter for Built-Out Self-Test of LPDDR5 김지희	view file link
2022	Design Techniques for Stochastic Frequency Detector Based Referenceless Clock and Data Recovery 최홍석	view file link
2022	Design of PAM4 Transmitter for PAM4-Binary Bridge 이언희	view file link
2022	Design of LC PLL for DDR5 Clock Buffer Application 이성준	view file link
2022	Ring-Oscillator-Based Frequency Synthesizers for High-Speed Serial Links 김효준	view file link

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