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Showing results 1 to 60 of 62

Issue Date	Title / Author(s) / Citation	File
1998	Reversible energy recovery logic circuit without non-adiabatic energy loss Lim, Junho; Kwon, Kipaek; Chae, Soo-Ik Electronics Letters- IEE, 1998, vol. 34, pp.344-346.	DOI
1998	Partial bus-invert coding for power optimization of system-level bus Shin, Youngsoo; Chae, Soo-Ik; Choi, Kiyoung International Symposium on Low Power Electronics and Design 1998, August 10-12, pp.127-132
1998	A cost-effective architecture for HDTV video decoder in ATSC receivers Kim, Jung-Min; Chae, Soo-Ik IEEE Trans. on Consumer Electronics, Vol. 44, No.4, pp.1353-1359	DOI
1998	New motion estimation algorithm using adaptively-quantized low bit resolution image and its VLSI architecture for MPEG2 video encoding Lee, Seongsoo; Kim, Jung-Min; Chae, Soo-Ik IEEE Trans. Circuits Syst. Video Technol., vol. 8, pp. 734-744	view file DOI
1998	Inceremental-search fast vector quantizer using triangular inequalities for multiple anchors Choi, Sunyoung; Chae, Soo-Ik Electronics Letters- IEE, 1998, 34, pp. 1192-1193
1998	Fast design of reduced complexity nearest-neighbor classifiers using triangular inequality Lee, Eelwan; Chae, Soo-Ik IEEE Trans. Pattern Anal. Mach. Intell., vol. 20, no. 5, pp. 562-566	view file DOI
1998-04	Reduction of bus transitions with partial bus-invert coding Shin, Young Soo; Chae, Soo-Ik; Choi, Kiyoung Electronics Letters- IEE, 1998, 34, (7), pp.642-643
1998-05	Analysis of the non-uniform samplings in sigma-delta modul ated signals Lee, Eelwan; Chae, Soo-Ik ISCAS '97	view file
1998-05	An HMM-MLP hybrid approach for improving discrimination in speech recognition Na, Kyungmin; Chae, Soo-Ik Proceedings of the International Joint Conference on Neural Networks, pp.156-159	view file
1998-08	New Motion Estimation Algorithm and Its Block-Matching Criteria Using Low-Resolution Quantization Lee, Seongsoo; Chae, Soo-Ik International Technical Conference on Circuits/Systems, Computers and Communications, pp.175-182	view file
1998-11	Simpler reversible energy recovery logic using NMOS switch networks with a cross-coupled PMOS pair Kwon, Kipaek; Chae, Soo-Ik Electronics Letters- IEE	view file DOI
1999	A 16-bit carry-lookahead adder using reversible energy recoverylogic for ultra-low-energy systems Lim, Junho; Kim, Donggyu; Chae, Soo-Ik IEEE J. Solid-State Circuits, vol. 34, pp. 898-903	DOI
1999	Hierarchical motion estimation in Hadamard transform domain Choi, Sunyoung; Chae, Soo-Ik Electronics Letters- IEE, 1999, 35, (25), pp. 2187-2188	DOI
1999	Reversible Energy Recovery logic circuits and its 8-phase clocked power generator for ultra-low-power applications Lim, Junho; Kim, Donggyu; Chae, Soo-Ik IEICE TRANSACTIONS on Electronics, Vol.E82-C, No.4, pp.646-653	view file
1999-10	Frequency-domain implementation of block adaptive filters for ICA-based multichannel blind deconvolution+I3055 Na, Kyungmin; Kang, Sangcheol; Lee, Kyungjin; Chae, Soo-Ik International Conference on Speech Processing, pp.455-460	view file
1999-12	Reduction in energy consumption by bootstrapped n MOS switches inreversible adiabatic CMOS circuits Lim, Junho; Kim, Donggyu; Chae, Soo-Ik IEE Proc., Circuits Devices Syst., 1999, 146, (6), pp. 327-333	DOI
2000	nMOS Reversible Energy Recovery Logic for Ultra-Low-Energy Applications Lim, Junho; Kim, Donggyu; Chae, Soo-Ik IEEE J. Solid-State Circuits, vol. 35, pp.865-875	view file DOI
2000	A 2 GHz CMOS Double Conversion Downconverter with Robust Image Rejection Performance against the Process and Temperature Variations Song, Eun-Seok; Chae, Soo-Ik; Kim, Wonchan VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on , vol., no., pp.38-41	view file DOI
2000-01	An 8 x 8 nRERL serial multiplier for ultra-low-power applications Lim, Joonho; Kim, Donggyu; Kang, Sangcheol; Chae, Soo-Ik Proc. of ASP-DAC'98, pp.35-36	view file
2000-04	Extended mean-distance-ordered search using multiple l1and l2 inequalities for fast vector quantization Choi, Sunyoung; Chae, Soo-Ik IEEE Trans. Circuits Syst. II, vol. 47, pp. 349-352	view file DOI
2000-06	Emulator environment based on an FPGA prototyping board Oh, Kyeongsu; Yoon, Sangyong; Chae, Soo-Ik IEEE International Workshop on Rapid System Prototyping, pp.72-77	view file
2000-07	A three-port nRERL register file for ultra-low-energy application Kwon, Junho; Lim, Joonho; Chae, Soo-Ik International Symposium on Low Power Electronics and Design, pp.155-160	view file
2001	Partial Bus-Invert Coding for Power Optimization of Application-Specific Systems Shin, Young Soo; Choi, Kiyoung; Chae, Soo-Ik IEEE Trans. VLSI Syst., vol. 9, pp.377-383	view file DOI
2001-06	A single-chip 2.4GHz direct-conversion CMOS transceiver with GFSK modem for bluetooth application Song, Eun-Seok; Kim, Jung-Min; Lim, Hyeong-Jun; Lee, Kyeongho; Chae, Soo-Ik; Jeong, Deog-Kyoon; Kim, Wonchan IEEE Symposium on VLSI Circuits, pp.245-246	view file
2001-12	An 8-b nRERL Microprocessor for Ultra-Low-Energy Applications Kim, Seokkee; Chae, Soo-Ik; Kwon, Jun-Ho Asia and South Pacific Design Automation Conference, pp.27-28	view file
2002-01	Two-step motion estimation algorithm for large search range usingoutlier pixel exclusion Lee, Seongsoo; Chae, Soo-Ik Electronics Letters- IEE, 2002, 38, (2), pp.68-69	DOI
2002-03	An efficient simulation environment for the design of networked Bluetooth devices Ahn, Yongjin; Kim, Dae Hong; Lee, Sunghyun; Park, Sanggyu; Yoo, Sung Joo; Choi, Kiyoung; Chae, Soo-Ik Design Automation for Embedded Systems, v.8, no. 2-3, pp. 119-138	DOI
2003	An efficient simulation environment and simulation techniques for Bluetooth device design Ahn, Yongjin; Kim, Dae Hong; Lee, Sunghyun; Park, Sanggyu; Yoo, Sung Joo; Choi, Kiyoung; Chae, Soo-Ik Design Automation for Embedded Systems, vol. 8, pp. 119-138	DOI
2003-09	A cycle-accurate joulemeter for CMOS VLSI circuits Song, Eun-Seok; Choi, Inchan; Park, Younggil; Chae, Soo-Ik European Solid-State Circuits Conference, pp.619-622	view file
2004	A 2.4GHz 0.25um CMOS Dual-Mode Direct-Conversion Transceiver for Bluetooth and 802.11b Jung, Yeon-Jae; Jeong, Hoesam; Song, Eunseok; Lee, Jungho; Lee, Seung-Wook; Seo, Donghyeon; Song, Inho; Jung, Sanghun; Park, Joonbae; Jeong, Deog-Kyoon; Chae, Soo-Ik; Kim, Wonchan IEEE J. Solid-State Circuits, vol.39, pp.1185-1190	DOI
2004	A reset-free anti-harmonic delay-locked loop using a cycle period detector Song, Eun-Seok; Chae, Soo-Ik; Lee, Seung-Wook; Lee, Jeong-Woo; Park, Joonbae IEEE J. Solid-State Circuits, vol. 39, pp. 2055-2061	DOI
2004	A Cycle-accurate Energy Estimator for CMOS Digital Circuits Song, Eun-Seok; Park, Younggil; Kwon, Soon; Chae, Soo-Ik Lecture Notes in Computer Science, vol.3254, pp.159-168	DOI
2004-06	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory Han, Sang-Il; Baghdadi, Amer; Bonaciu, Marius Petru; Chae, Soo-Ik; Jerraya, Ahmed Amine Design Automation Conference, pp.250-255	view file
2005	A 0.25um CMOS Quad-Band GSM RF Transceiver using an Efficient LO Frequency Plan Song, Eun-Seok; Lee, Deok-Hee; Chu, Sang Young; Chae, Soo-Ik; Koo, Yido; Jung, Yeon-Jae IEEE J. Solid-State Circuits, vol. 40, pp. 1094-1106	DOI
2005-01	A fast VLSI architecture for full-search variable block size motion estimation in MPEG--4 AVC/H.264 Kim, Minho; Hwang, Ingu; Chae, Soo-Ik Asia and South Pacific Design Automation Conference, pp.613-615	view file
2005-05	Implementation of a simple 8-bit microprocessor with reversible energy recovery logic Kim, Seokkee; Chae, Soo-Ik Conference On Computing Frontiers, pp.421-426
2005-06	A C/C++-based functional verification framework using the SystemC verification library_ Park, Sanggyu; Chae, Soo-Ik 16th IEEE International Workshop on Rapid System Prototyping (RSP '05), pp.237-239	view file
2005-06	A two-week program for platform-based SoC design Park, Sanggyu; Chae, Soo-Ik International Conference on Microelectronic Systems Education, pp.43-44	view file
2005-08	Complexity reduction in an nRERL microprocessor Kim, Seokkee; Chae, Soo-Ik International Symposium on Low Power Electronics and Design, pp.180-185
2006-01	Reusable Component IP Design using Refinement-based Design Environment Park, Sanggyu; Yoon, SangYong; Chae, Soo-Ik Asia and South Pacific Design Automation Conference, pp.588-593	view file
2006-01	Functional modeling techniques for efficient SW code generation of video codec applications Han, SangIl; Chae, Soo-Ik; Jerraya, Ahmed. A. Asia and South Pacific Design Automation Conference, pp.74-85
2006-06	A mixed-level virtual prototyping environment for refinement-based design environment Park, Sanggyu; Yoon, SangYong; Chae, Soo-Ik IEEE International Workshop on Rapid System Prototyping (RSP '06), pp.63-68	view file
2006-07	Buffer memory optimization for video codec application modeled in simulink Han, SangIl; Guerin, Xavier; Chae, Soo-Ik; Jerraya, Ahmed. A Design Automation Conference 2006, pp.689-694
2006-09	Implementation of an OpenVG Rasterizer with Configurable Anti-aliasing and Multi-window Scissoring Huang, Ren; Chae, Soo-Ik IEEE International Conference on Computer and Information Technology, pages 179-184	view file
2006-12	Implementation of a H.264 decoder with Template-based Communication Refinement Yoon, SangYong; Park, Sanggyu; Chae, Soo-Ik IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2006), pp.571-574	view file
2007	Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC Han, Sang-Il; Brisolara, Lisane; Carro, Luigi; Reis, Ricardo; Guerin, Xavier; Jerraya, Ahmed Amine; Chae, Soo-Ik Design Automation for Embedded Systems 11(4):249-283	DOI
2007-04	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC Brisolara, Lisane; Han, SangIl; Guerin, Xavier; Carro, Luigi; Reis, Ricardo; Chae, Soo-Ik; Jerraya, Ahmed 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2007), pp.81-89	view file
2007-06	Simulink-Based MPSoC design flow: case study of motion-JPEG and h.264 Huang, Kai; Han, SangIl; Popovici, Katalin; Brisolara, Lisane; Guerin, Xavier; Li, Lei; Yan, Xiaolang; Chae, Soo-Ik; Carro, Luigi; Jerraya, Ahmed Amine Design Automation Conference 2007, pp.39-42
2007-07	Hardware implementation of inter-processor communication in MPSoCs for multimedia applications Koo, Moonmo; Chae, Soo-Ik International Technical Conference on Circuits/Systems, Computers and Communications	view file
2007-12	Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC Han, Sang-Il; Chae, Soo-Ik; Brisolara, Lisane; Guerin, Xavier; Reis, Ricardo; Carro, Luigi; Jerraya, Ahmed Amine DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, Vol.11, No.4, pp.249-283	view file DOI
2008	A High-Performance OpenVG Accelerator with Dual-Scanline Filling Rendering Kim, Daewoong; Cha, Kilhyung; Chae, Soo-Ik IEEE Transactions on Consumer Electronics, vol. 54, pp.1303-1311	DOI
2008-05	A hardware operating system kernel for multi-processor systems Park, Sanggyu; Hong, Do-sun; Chae, Soo-Ik IEICE Electron. Express, 5(9), pp.296-302	DOI
2008-09	RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow Cho, Jinhyun; Choi, Soonwoo; Chae, Soo-Ik Forum on specification and Design Languages 2008, pp.251-252	view file
2008-11	High performance IPC hardware accelerator and communication network for MPSoCs Koo, Moonmo; Chae, Soo-Ik International SoC Design Conference, Vol.3 CDC Session pp.21-22	view file
2008-11	An Optimized Rendering Algorithm for Hardware Implementation of OpenVG 2D Vector Graphics Cha, Kilhyung; Kim, Daewoong; Chae, Soo-Ik International SoC Design Conference, Vol.1 ORAL Session pp.338-341	view file
2008-12	Cache Optimization for H.264/AVC Motion Compensation Yoon, Sangyong; Chae, Soo-Ik IEICE Trans. Information and Systems, vol. E91-D no. 12 pp.2902-2905	view file
2008-12	Cache Optimization for H.264/AVC Motion Compensation Yoon, Sangyong; Chae, Soo-Ik IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS; Vol.E91D, No.12, pp.2902-2905	view file DOI
2009	Simulink(R)-based heterogeneous multiprocessor SoC design flow for mixed Hardware/Software refinement and Simulation Han, Sang-Il; Chae, Soo-Ik; Brisolara, Lisane; Carro, Luigi; Popovici, Katalin; Guerin, Xavier; Jerraya, Ahmed A.; Huang, Kai; Li, Lei; Yan, Xiaolang Integration, the VLSI Journal 42 pp.227-245	DOI
2009	A mixed-level virtual prototyping environment for SystemC-based design methodology Park, Sanggyu; Yoon, Sangyong; Chae, Soo-Ik Microelectronics Journal. 40(7) 1082-1093.	DOI
2009-01	VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications Cho, Jinhyun; Yoon, Sangyong; Park, Sanggyu; Lee, Doowon; Chae, Soo-Ik IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Vol.E92A, No.1, pp.279-290	view file DOI

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